參數(shù)資料
型號： DAC1617D1G0HN
廠商： NXP Semiconductors N.V.
元件分類： 外設(shè)及接口
英文描述： Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
封裝： DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813
文件頁數(shù)： 52/66頁
文件大小： 519K
代理商： DAC1617D1G0HN
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10.18.6
Page A register allocation map
D
A
O
R
5
N
D
D
Table 50
shows an overview of all registers on page A (0Ah in hexadecimal).
Table 50.
Address
Page_0A register allocation map
Register name
R/W
Bit definition
Bit 4
LD_PD
Default
Bin
0000
0011
0000
0000
0000
0000
0011
1111
0010
0000
0001
1110
0000
0000
0000
0000
0000
0011
0000
0000
0000
0000
0100
0000
0000
0000
0100
0000
0011
1010
Bit 7
-
Bit 6
-
Bit 5
-
Bit 3
Bit 2
CAL_
CNTRL
LDCLK_DEL[3:0]
Bit 1
RST_
DCKL
Bit 0
RST_
LCKL
Hex
03h
0
00h
MAIN_CNTRL
R/W
PD_CNTRL
1
01h
MAN_LDCLKDEL
R/W
-
-
-
-
00h
2
02h
DBG_LVDS
R/W
-
-
-
-
SBER
RESERVED
00h
4
04h
RST_EXT_LDCLK
R/W
RST_EXT_LCLK_TIME[7:0]
3Fh
5
05h
RST_EXT_DCLK
R/W
RST_EXT_DCLK_TIME[7:0]
20h
6
06h
DCMSU_PREDIV
R/W
DCMSU_PREDIVIDER[7:0]
1Eh
8
08h
LD_POL_LSB
R/W
LD_POL[7:0]
00h
9
09h
LD_POL_MSB
R/W
LD_POL[15:8]
00h
10
0Ah
LD_CNTRL
R/W
PARITYC DESCRAMBLE
SEL_EN[1:0]
WORD_SWAP
LDAB_
SWAP
IQ_
FORMAT
CDI_MODE[1:0]
EDGE_
LDCLK
03h
11
0Bh
MISC_CNTRL
R/W
SR_CDI
RESERVED
I_LEV_
CNTRL[1:0]
Q_LEV_CNTRL[1:0]
00h
12
0Ch
I_DC_LVL_LSB
R/W
I_DC_LEVEL[7:0]
00h
13
0Dh
I_DC_LVL_MSB
R/W
I_DC_LEVEL[15:8]
20h
14
0Eh
Q_DC_LVL_LSB
R/W
Q_DC_LEVEL[7:0]
00h
15
0Fh
Q_DC_LVL_MSB
R/W
Q_DC_LEVEL[15:8]
20h
27
1Bh
TYPE_ID
R
DAC
FRONTEND[1:0]
DUAL
DSP[1:0]
BIT_RES[1:0]
3Ch
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