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| 型號： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 49/66頁 |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
49 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 42.
Default values are shown highlighted.
Bit
Symbol
4 to 0
MDS_OFFSET_DLY[6:0]
MDS_OFFSET_DLY register (address 07h) bit description
Access
R/W
Value
-
Description
delay offset for dataflow (two’s complement [
16 to 15]
Table 43.
Default values are shown highlighted.
Bit
Symbol
6 to 0
MDS_ADJDELAY[6:0]
MDS_ADJDELAY register (address 08h) bit description
Access
R
Value
-
Description
actual value adjustment delay
Table 44.
Default values are shown highlighted.
Address
Register
09h
MDS_STATUS0
MDS status registers (address 09h to 0Ah) bit description
Bit
7
Symbol
EARLY
Access
R
Value
Description
early signal (sampled) from
early-to-late detector
false
true
late signal (sampled) from
early-to-late detector
false
true
equal signal (sampled) from
early-to-late detector
false
true
result equal-check
false
true
adjustment delay maximum value
stops the search
false
true
adjustment delay minimum value
stops the search
false
true
evaluation logic has detected equal
condition
false
true
evaluation logic active
false
true
0
1
6
LATE
R
0
1
5
EQUAL
R
0
1
4
MDS_LOCK
R
0
1
3
EARLY_ERROR
R
0
1
2
LATE_ERROR
R
0
1
1
EQUAL_FOUND
R
0
1
0
MDS_ACTIVE
R
0
1
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