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| 型號： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 8/66頁 |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
8 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
9. Characteristics
Table 5.
V
DDA(1V8)
= 1.8 V; V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
= 3.3 V; Typical values measured at T
amb
= +25
C; R
L
= 50
; I
O(fs)
= 20 mA;
maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition
defined in
Figure 22
; output level = 1 V (p-p).
Symbol
Parameter
Conditions
Test
[1]
Characteristics
Min
Typ
Max
Unit
V
DDA(3V3)
analog supply
voltage (3.3 V)
digital supply
voltage (1.8 V)
analog supply
voltage (1.8 V)
analog supply
current (3.3 V)
digital supply
current (1.8 V)
C
3.15
3.3
3.45
V
V
DDD(1V8)
C
1.7
1.8
1.9
V
V
DDA(1V8)
C
[2]
1.7
1.8
1.9
V
I
DDA(3V3)
Auxiliary DAC on
C
59
62
66
mA
I
DDD(1V8)
f
s
= 983.04 67;
4 interpolation; no NCO;
MDS on
f
s
= 620 Msps;
2 interpolation; NCO on;
no MDS
f
s
= 983.04 Msps; 1 V (p-p) C
f
s
= 620 Msps; 1 V (p-p)
f
s
= 983.04 Msps;
4 interpolation; NCO off;
MDS off
f
s
= 983.04 Msps;
4 interpolation;
5-bit NCO; MDS off
f
s
= 620 Msps;
2 interpolation; 40-bit
NCO; MDS off
power-down using SPI
register
C
465
520
580
mA
C
385
435
485
mA
I
DDA(1V8)
analog supply
current (1.8 V)
[2]
200
205
-
226
226
<tbd>
240
250
-
mA
mA
mW
C
C
P
tot
total power
dissipation
C
-
1690
-
mW
-
1400
-
mW
C
-
66
-
mW
Clock inputs (pins CLKP, CLKN)
V
i(clk)dif
differential clock
input voltage
R
i
input resistance
C
i
input
capacitance
Digital inputs (pins LD[15]P to LD[0]P, LD[15]N to LD[0]N, LCKP and LCKN, ALIGNP and ALIGNN)
V
i
input voltage
V
gpd
< 50 mV
[3]
V
idth
input differential
threshold
voltage
R
i
input resistance
C
i
input
capacitance
peak-to-peak
C
150
-
1000
mV
D
D
-
-
200
0.6
-
-
k
pF
C
C
825
100
-
-
1575
+100
mV
mV
V
gpd
< 50 mV
[3]
D
D
-
-
100
0.8
-
-
pF
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