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| 型號(hào)： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 55/66頁 |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
55 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 54.
Default values are shown highlighted.
Address
Register
04h
RST_EXT_LCLK
Extension time reset registers (address 04h to 05h) bit description
Bit
7 to 0
Symbol
RST_EXT_LCLK_
TIME[7:0]
Access
R/W
Value
Description
specifies extension time reset,
expressed in LVDS clock periods
8 bits for the extension time reset
specify extension time reset,
expressed in DCLK periods
8 bits for the extension time reset
-
05h
RST_EXT_DCLK
7 to 0
RST_EXT_DCLK_
TIME[7:0]
R/W
-
Table 55.
Default values are shown highlighted.
Bit
Symbol
7 to 0
DCMSU_PREDIVIDER[7:0]
Register DCSMU_PREDIV (address 06h)
Access
R/W
Value
Description
predivider value for the DCMSU, expressed in LVDS
clock period
8 bits for the predivider value
-
Table 56.
Default values are shown highlighted.
Address
Register
08h
LD_POL_LSB
LSB/MSB of polarity registers (address 08h to 09h) bit description
Bit
7 to 0
Symbol
LD_POL[7:0]
Access
R/W
Value
Description
toggles polarity of corresponding bit
pair within LD[7:0]
most significant 6 bits for the
polarity toggle
most significant 6 bits for the
polarity toggle
-
09h
LD_POL_MSB
7 to 0
LD_POL[15:8]
-
Table 57.
Default values are shown highlighted.
Bit
Symbol
7
PARITYC
Register LD_CNTRL (address 0Ah)
Access
R/W
Value
Description
parity check
disable
enable
Descramble control
disable descrambling
enable descrambling
LDVS data enable
LDVS data enable = align signal from channel A
LDVS data enable = align signal from channel B
LDVS data enable = 0
LDVS data enable = 1
reverse order for LVDS path
normal operation
MSB to LSB order reversed
0
1
6
DESCRAMBLE
R/W
0
1
5 to 4
SEL_EN[1:0]
R/W
00
01
10
11
3
WORD_SWAP
R/W
0
1
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