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| 型號(hào)： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁(yè)數(shù)： | 21/66頁(yè) |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
21 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
The compensation delay time, referred to as t
cmp
in
Figure 14
, can be tuned automatically
or manually.
Automatic tuning is recommended for a high-speed LVDS data rate (> 300 MHz). The
external LVDS data and clock signals aligns the rising and falling edges. The timing
requirement is defined in
Figure 15
and in
Table 5
.
When tuning manually, the compensation delay time (t
cmp
in
Figure 14
), can be tuned as
shown in
Table 11
using bits LDCLK_DEL[3:0] of register MAN_LDCLKDEL
(see
Table 52
) and bit CAL_CNTRL of register MAIN_CNTRL (see
Table 51
).
Fig 14. LVDS DDR demux timing (LVDS A and B paths not swapped; LDAB_SWAP = 0)
t
sk(min)
= minimum skew time
t
sk(max)
= maximum skew time
Fig 15. Timing requirement automatic tuning
001aan400
D
n
[i]
D
n
[i]
D
n + 1
[i]
D
n + 1
[i]
D
n + 3
[i]
D
n
1
[i]
t
cmp
D
n
1
[i]
D
n + 2
[i]
D
n + 2
[i]
LDCLKN
LDCLKP
LD[i]N
LD[i]P
LDCLKNcp
LDCLKPcp
LDA[i]
LDB[i]
001aan833
LVDS data
LVDS clock
V
IH
V
IL
V
IH
V
IL
t
sk(min)
t
sk(max)
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