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| 型號(hào)： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 22/66頁 |
| 文件大小： | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
22 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
Table 11.
LDCLK_DEL[3:0]
10.7 Operating modes
The DAC1617D1G0 requires two differential clocks:
The LVDS clock (LDCLKP, LDCLKN) for the LVDS DDR interface
The data
clock (CLKP, CLKN) for the internal PLL and the dual DAC core
Set the Clock Domain Interface (CDI) and the PLL correctly to configure the
DAC1617D1G0 for an application mode. The default application is a
2 upsampling mode
(see
Section 10.7.1
). The CDI can also support
4 and
8 upsampling modes
(see
Section 10.7.2
and
Section 10.7.3
).
10.7.1
CDI mode 0 (x2 interpolation)
CDI mode 0 (
2 interpolation) is required when the value of the LVDS DDR clock is twice
the internal maximum CDI frequency.
Table 12
shows examples of applications using an
internal PLL or an external clock for the DAC core.
Compensation delay values for manual tuning
CAL_CNTRL
Typical compensation delay
time
t
cmp
controlled by DCSMU
block (automatic control)
360 ps to 405 ps
435 ps to 540 ps
525 ps to 645 ps
600 ps to 720 ps
690 ps to 825 ps
780 ps to 900 ps
885 ps to 1035 ps
960 ps to 1200 ps
1260 ps to 1980 ps
1350 ps to 2160 ps
1440 ps to 2340 ps
1512 ps to 2556 ps
1566 ps to 2754 ps
1620 ps to 2952 ps
1674 ps to 3060 ps
1710 ps to 3186 ps
xxx
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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