參數(shù)資料
型號(hào)： DAC1617D1G0HN
廠商： NXP Semiconductors N.V.
元件分類： 外設(shè)及接口
英文描述： Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
封裝： DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813
文件頁數(shù)： 65/66頁
文件大?。?/td> 519K
代理商： DAC1617D1G0HN
DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
65 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
17. Tables
Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Table 3. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .7
Table 4. Thermal characteristics . . . . . . . . . . . . . . . . . . .7
Table 5. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 6. Read or Write mode access description . . . . .14
Table 7. Number of bytes transferred . . . . . . . . . . . . . .14
Table 8. SPI timing characteristics . . . . . . . . . . . . . . . .15
Table 9. Input LVDS bus swapping . . . . . . . . . . . . . . . .17
Table 10. Folded and interleaved format mapping. . . . . .18
Table 11. Compensation delay values for manual
tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 12. CDI mode 0: operating modes examples . . . .23
Table 13. CDI mode 1: operating modes examples . . . .23
Table 14. CDI mode 2: operating modes examples . . . .24
Table 15: Interpolation filter coefficients . . . . . . . . . . . . .25
Table 16. Complex modulator operation mode . . . . . . . .27
Table 17. Inversion filter coefficients . . . . . . . . . . . . . . . .28
Table 18. DAC transfer function . . . . . . . . . . . . . . . . . . .29
Table 19. Digital offset adjustment . . . . . . . . . . . . . . . . .30
Table 20. Auxiliary DAC transfer function . . . . . . . . . . . .32
Table 21. Page_00 register allocation map . . . . . . . . . . .38
Table 22. Register COMMON (address 00h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 23. Register TXCFG (address 01h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 24. Register PLLCFG (address 02h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 25. NCO frequency registers
(address 04h to 08h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .41
Table 26. DAC output phase correction registers
(address 09h to 0Ah) bit description . . . . . . . .42
Table 27. Digital gain control registers
(address 0Bh to 0Eh) bit description . . . . . . . .42
Table 28. Register DAC_OUT_CTRL (address 0Fh) . . .42
Table 29. Register DAC_CLIPPING (address 10h) . . . . .43
Table 30. Digital offset value registers
(address 11h to 14h) bit description . . . . . . . . .43
Table 31. NCO phase offset registers
(address 15h to 16h) bit description . . . . . . . .43
Table 32. Analog gain control registers
(address 17h to 1Ah) bit description . . . . . . . .44
Table 33. Auxiliary DAC registers
(address 1Bh to 1Eh) bit description . . . . . . . .44
Table 34. SPI_PAGE register (address 1Fh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 35. Page 1 register allocation map . . . . . . . . . . . .45
Table 36. MDS_MAIN register (address 00h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 37. MDS window time registers
(address 01h to 02h) bit description . . . . . . . .47
Table 38. MDS_MISCCNTRL0 register
(address 03h) bit description . . . . . . . . . . . . . .47
Table 39. MDS_MAN_ADJUSTDLY register
(address 04h) bit description . . . . . . . . . . . . . .48
Table 40. MDS_AUTO_CYCLES register
(address 05h) bit description . . . . . . . . . . . . . . 48
Table 41. MDS_MISCCNTRL1 register
(address 06h) bit description . . . . . . . . . . . . . . 48
Table 42. MDS_OFFSET_DLY register
(address 07h) bit description . . . . . . . . . . . . . . 49
Table 43. MDS_ADJDELAY register
(address 08h) bit description . . . . . . . . . . . . . . 49
Table 44. MDS status registers
(address 09h to 0Ah) bit description . . . . . . . . 49
Table 45. Bias current control registers
(address 0Eh to 15h) bit description . . . . . . . . 50
Table 46. Bias current control table . . . . . . . . . . . . . . . . 50
Table 47. DAC_PON_SLEEP register
(address 16h) bit description . . . . . . . . . . . . . . 51
Table 48. DAC_TEST_8 register
(address 17h) bit description . . . . . . . . . . . . . . 51
Table 49. SPI_PAGE register
(address 1Fh) bit description . . . . . . . . . . . . . 51
Table 50. Page_0A register allocation map . . . . . . . . . . 52
Table 51. Register MAIN_CNTRL (address 00h) . . . . . . 54
Table 52. Register MAN_LDCLKDEL (address 01h) . . . 54
Table 53. Register DBG_LVDS (address 02h) . . . . . . . . 54
Table 54. Extension time reset registers
(address 04h to 05h) bit description . . . . . . . . 55
Table 55. Register DCSMU_PREDIV (address 06h) . . . 55
Table 56. LSB/MSB of polarity registers
(address 08h to 09h) bit description . . . . . . . . 55
Table 57. Register LD_CNTRL (address 0Ah) . . . . . . . . 55
Table 58. Register MISC_CNTRL (address 0Bh) . . . . . . 56
Table 59. LDS/MDS of I/Q DC levels registers
(address 0Ch to 0Fh) bit description . . . . . . . . 57
Table 60. Register TYPE_ID (address 1Bh) . . . . . . . . . . 57
Table 61. Register DAC_VERSION (address 1Ch) . . . . 57
Table 62. Register DIG_VERSION (address 1Dh) . . . . . 57
Table 63. Register LVDS_VERSION (address 1Eh) . . . . 58
Table 64. Register PAGE_ADD (address 1Fh) . . . . . . . . 58
Table 65. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 66. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 62
相關(guān)PDF資料
PDF描述
DAC1627D1G25HN Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating
DAC1627D1G25
DAC1627D1G25HN Dual 16-bit DAC, up to 1.25 Gsps; 2x 4x and 8x interpolating
DAN2222E SWITCHING DIODE
DCX100NS 100mA DUAL COMPLEMENTARY PRE-BIASED TRANSISTORS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DAC1617D1G0HN-C1 制造商:Integrated Device Technology Inc 功能描述:HVQFN72 - Bulk
DAC1617D1G0HN-C18 制造商:Integrated Device Technology Inc 功能描述:HVQFN72 - Tape and Reel
DAC1617D1G0IQM-DB 制造商:Integrated Device Technology Inc 功能描述:BOARD - Boxed Product (Development Kits)
DAC161K87B WAF 制造商:ON Semiconductor 功能描述:
DAC161P997 制造商:TI 制造商全稱:Texas Instruments 功能描述:DAC161P997 Single-Wire 16-bit DAC for 4-20mA Loops
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*