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| 型號(hào)： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁(yè)數(shù)： | 20/66頁(yè) |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
20 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.6 Timing
The DAC1617D1G0 can operate at an update rate (f
s
) of up to 1 Gsps and with an input
data rate (f
data
) of up to 312.5 MHz.
The sampling position of the LVDS data can be tuned using a 16-step compensation delay
clock. The delay clock (see
Figure 14
, signals LDCLKPcp and LDCLKNcp) is used
internally to obtain a control signal. This enables calibrating the compensation delay at
start-up and monitoring if the sampling position is properly aligned.
Figure 14
shows how the compensation delay helps to recover the LVDS DDR data on
both the A and B paths.
Fig 12. DAC core clock: CML configuration with AC-coupling
Fig 13. DAC core clock: PECL configuration with AC-coupling
aaa-000257
Z = 50 Ω
50 Ω
DAC1617D
Z = 50 Ω
CML
3.3 V
50 Ω
3.3 V
CLKP
CLKN
100 nF
100 nF
aaa-000258
Z = 50 Ω
100 Ω
CLKN
200 Ω
200 Ω
DAC1617D
Z = 50 Ω
PECL
CLKP
100 nF
100 nF
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