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| 型號： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 19/66頁 |
| 文件大小： | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
19 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
10.5 Input clock
The DAC1617D1G0 operates with two clocks, one for the LVDS DDR interface and one
for the DAC core.
10.5.1
LVDS DDR clock
The LVDS DDR clock can be interfaced as shown in
Figure 10
because the clock buffer
contains a 100
internal resistor.
10.5.2
DAC core clock
The DAC core clock can achieve a frequency of up to 1 Gsps. It includes internal biasing
to support both AC-coupling and DC-coupling. The clock can be easily connected to any
LVDS, CML or PECL clock sources.
Depending on the interface selected, the hardware configuration varies
(see
Figure 11
to
Figure 13
).
Fig 10. LVDS DDR clock configuration
aaa-000254
Z = 100 Ω
100 Ω
DAC1617D
LVDS
LCLKP
LCLKN
LVDS
a. DC-coupling
b. AC-coupling
Fig 11. DAC core clock: LVDS configuration
aaa-000256
Z = 100 Ω
100 Ω
LVDS
CLKP
CLKN
DAC1617D
aaa-000255
Z = 100 Ω
100 Ω
LVDS
CLKP
CLKN
DAC1617D
100 nF
100 nF
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