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參數(shù)資料
| 型號： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 56/66頁 |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
56 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
2
LDAB_SWAP
R/W
swaps LVDS A and LVDS B paths
normal operation
LVDS A and LVDS B paths are swapped
specify IQ supplied format
folded
interleaved
specify sampling edge for LVDS data path
falling edge of LDCLK
rising edge of LDCLK
0
1
1
IQ_FORMAT
R/W
0
1
0
EDGE_LDCLK
R/W
0
1
Table 57.
Default values are shown highlighted.
Bit
Symbol
Register LD_CNTRL (address 0Ah)
…continued
Access
Value
Description
Table 58.
Default values are shown highlighted.
Bit
Symbol
7
SR_CDI
Register MISC_CNTRL (address 0Bh)
Access
R/W
Value
Description
CDI block software reset control
no action
perform a software reset on CDI
reserved
specifies output from CDI for I path
normal operation (CDI data output sent to digital
signal processing input)
if LDVS data enable = 1, then normal operation; if
LDVS data enable = 0, then digital signal processing
input = I_DC_LEVEL register value
digital signal processing input = I_DC_LEVEL
digital signal processing input = I_DC_LEVEL
specifies output from CDI for Q path
normal operation (CDI data output sent to digital
signal processing input)
if LDVS data enable = 1, then normal operation; if
LDVS data enable = 0, then digital signal processing
input = Q_DC_LEVEL register value
digital signal processing input = Q_DC_LEVEL
digital signal processing input = Q_DC_LEVEL
specifies CDI mode
cdi_mode 0 (
2 mode)
cdi_mode 1 (
4 mode)
cdi_mode 2 (
8 mode)
not used
0
1
0
6
5 to 4
RESERVED
I_LEV_CNTRL[1:0]
R/W
R/W
00
01
10
11
3 to 2
Q_LEV_CNTRL[1:0]
R/W
00
01
10
11
1 to 0
CDI_MODE[1:0]
R/W
00
01
10
11
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