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| 型號： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁數(shù)： | 14/66頁 |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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DAC1617D1G0
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1.1 — 30 September 2011
14 of 66
NXP Semiconductors
DAC1617D1G0
Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating
R/W indicates the mode access (see
Table 6
)
Table 6.
R/W
0
1
Table 7
shows the number of bytes to be transferred. N1 and N0 indicate the number of
bytes transferred after the instruction byte.
Table 7.
N1
0
0
1
1
A[4:0] indicates which register is being addressed. If a multiple transfer occurs, this
address concerns the first register. The other registers follow directly in a decreasing
order (see
Table 21
,
Table 35
and
Table 50
).
The DAC1617D1G0 incorporates more than the 32 SPI registers allowed by the address
value A[4:0]. It uses three SPI register pages (page_00, page_01, and page_0A), each
containing 32 registers. The 32
nd
register of each page indicates which page is currently
addressed (00h, 01h or 0Ah).
Fig 3.
SPI protocol
001aan829
RESET_N
(optional)
SCS_N
SCLK
SDIO
SDO
(optional)
R/W
N1
N0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Read or Write mode access description
Description
Write mode operation
Read mode operation
Number of bytes transferred
N0
0
1
0
1
Number of bytes transferred
1 byte
2 bytes
3 bytes
4 bytes
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