
PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
16
the External Oscillator Enable (Bit 0, Figure 9-2) will be cleared by a WDR, but it does not take effect until suspend mode is
entered.
7. The Program Stack Pointer (PSP) and Data Stack Pointer (DSP) reset to address 0x00. (Firmware should move the DSP for
USB applications, as explained in Section 6.5.)
8. Program execution begins at address 0x0000 (after the appropriate time-out period).
10.1
Low Voltage Reset (LVR)
The CY7C637xx enters a partial suspend state when VCC is first applied to the chip. The internal oscillator is started and the Low
Voltage Reset (LVR) signal is initially asserted at power-up until VCC has risen above VLVR. At that point, the LVR is deasserted
and an internal counter starts counting. After tSTART the partial suspend state ends and program execution begins from address
0x0000. This provides time for VCC to stabilize before the part executes code.
As long as the LVR is enabled, this reset sequence repeats whenever the VCC pin voltage drops below VLVR. The LVR can be
disabled by firmware by setting the Low Voltage Reset Disable bit in the Clock Configuration Register. In addition, the LVR is
automatically disabled in suspend mode to save power. LVR becomes active again (if enabled) once the suspend mode ends.
Whenever LVR is disabled (i.e. by firmware or during suspend mode), a secondary low-voltage monitor (BOR) is active, as
described in the next section. The LVR/BOR bit, bit 4 of the Processor Status and Control Register (20-1), is set to “1” to indicate
that one of these resets has occurred.
10.2
Brown Out Reset (BOR)
The Brown Out Reset (BOR) circuit is active whenever LVR is disabled. BOR is asserted whenever the VCC voltage to the device
is below an internally defined trip voltage of approximately 2.5V. This reset behaves like LVR, and in addition re-enables the LVR.
That is, once VCC drops and trips BOR, the part remains in reset until VCC rises above VLVR. At that point, the tSTART delay occurs
before normal operation (from reset) resumes.
In suspend mode, only the BOR detection is active, giving a reset if VCC drops below approximately 2.5V. Since the device is
suspended and code is not executing, this lower voltage is safe for retaining the state of all registers and memory.
10.3
Watch Dog Reset (WDR)
The Watch Dog Timer Reset (WDR) occurs when the internal Watch Dog timer rolls over. Writing any value to the write-only
Watch Dog Restart Register at address 0x26 will clear the timer. The timer will roll over and WDR will occur if it is not cleared
within tWATCH (10 ms minimum) of the last clear. Bit 6 of the Processor Status and Control Register is set to record this event (the
register contents are set to 010X0001 by the WDR). A Watch Dog Timer Reset lasts for 2–4 ms after which the microcontroller
begins execution at ROM address 0x0000. The clock mode (internal or external) is not changed by a WDR.
Figure 10-1. Watch Dog Reset (WDR)
11.0
Suspend Mode
The CY7C637xx parts support a versatile low-power suspend mode. In suspend mode, only an enabled interrupt or a LOW state
on the D–/SDATA pin will wake the part. Two options are available. For lowest power, all internal circuits can be disabled, so only
an external event will resume operation. Alternately, a low-power internal wake-up timer can be used to trigger the wake-up
interrupt. This timer is described in Section 11.2, and can be used to periodically poll the system to check for changes, such as
looking for movement in a mouse, while maintaining a low average power.
The CY7C637xx is placed into a low-power state by setting the Suspend bit of the Processor Status and Control Register (Figure
20-1). All logic blocks in the device are turned off except the GPIO interrupt logic, the D–/SDATA pin input receiver, and (optionally)
the wake-up timer. The clock oscillators, as well as the free-running and watch dog timers are shut down. Only the occurrence of
At least 10.1 ms
WDR goes HIGH
Execution begins at
ROM Address 0x0000
10.1 to
2–4 ms
since last write to WDT
for 2–4 ms
14.6 ms
(at FOSC = 6 MHz)
WDR