參數(shù)資料
型號： CY7C63742-SC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24
封裝： 0.300 INCH, PLASTIC, SOIC-24
文件頁數(shù)： 34/48頁
文件大?。?/td> 425K
代理商： CY7C63742-SC
PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
4
LIST OF FIGURES (continued)
Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses 0x14, 0x16) .......................... 23
Figure 14-4. USB Device Counter Registers (Addresses 0x11h, 0x13h, 0x15) ............................ 23
Figure 16-1. Diagram of USB - PS/2 System Connections ............................................................. 25
Figure 17-1. SPI Block Diagram ........................................................................................................ 26
Figure 17-2. SPI Data Register (Address 0x60) ............................................................................... 26
Figure 17-3. SPI Control Register (Address 0x61) .......................................................................... 27
Figure 17-4. SPI Data Timing ............................................................................................................ 28
Figure 18-1. Timer LSB Register (Address 0x24) ........................................................................... 29
Figure 18-2. Timer MSB Register (Address 0x25) ........................................................................... 29
Figure 18-3. Timer Block Diagram .................................................................................................... 29
Figure 19-1. Capture Timers Block Diagram ................................................................................... 30
Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40) ........................................... 31
Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41) ........................................... 31
Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42) ........................................... 31
Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43) ........................................... 31
Figure 19-6. Capture Timers Configuration Register (Address 0x44) .......................................... 31
Figure 19-7. Capture Timers Status Register (Address 0x45) ....................................................... 31
Figure 20-1. Processor Status and Control Register (Address 0xFF) .......................................... 32
Figure 21-1. Global Interrupt Enable Register 0x20h (read/write) ................................................. 33
Figure 21-2. USB End Point Interrupt Enable Register (Address 0x21) ....................................... 33
Figure 21-3. Interrupt Controller Logic Block Diagram .................................................................. 34
Figure 21-4. Port 0 Interrupt Enable Register (Address 0x04) ....................................................... 36
Figure 21-5. Port 1 Interrupt Enable Register (Address 0x05) ....................................................... 36
Figure 21-6. Port 0 Interrupt Polarity Register (Address 0x06) ..................................................... 36
Figure 21-7. Port 1 Interrupt Polarity Register (Address 0x07) ..................................................... 36
Figure 21-8. GPIO Interrupt Diagram ............................................................................................... 36
Figure 25-1. Clock Timing ................................................................................................................. 43
Figure 25-2. USB Data Signal Timing ............................................................................................... 43
Figure 25-3. Receiver Jitter Tolerance ............................................................................................. 44
Figure 25-4. Differential to EOP Transition Skew and EOP Width ................................................ 44
Figure 25-5. Differential Data Jitter .................................................................................................. 44
Figure 25-7. SPI Slave Timing, CPHA=0 .......................................................................................... 45
Figure 25-6. SPI Master Timing, CPHA=0 ........................................................................................45
Figure 25-8. SPI Master Timing, CPHA=1 ........................................................................................46
Figure 25-9. SPI Slave Timing, CPHA=1 .......................................................................................... 46
LIST OF TABLES
Table 8-1. I/O Register Summary ...................................................................................................... 13
Table 11-1. Wake-up Timer Adjust Settings .................................................................................... 18
Table 12-1. Ports 0 and 1 Output Control Truth Table ................................................................... 19
Table 13-1. Control Modes to Force D+/D– Outputs ....................................................................... 22
Table 17-1. SPI Control Register Definitions ................................................................................... 27
Table 17-2. SPI Pin Assignments ..................................................................................................... 28
Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz) ............ 32
Table 21-1. Interrupt Vector Assignments ....................................................................................... 34
Table 22-1. USB Register Mode Encoding ...................................................................................... 37
Table 22-2. Decode table for Table 22-3: “Details of Modes for Differing Traffic Conditions” ... 38
Table 22-3. Details of Modes for Differing Traffic Conditions .......................................................39
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