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參數(shù)資料
| 型號(hào)： | CY7C63742-SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 425K |
| 代理商： | CY7C63742-SC |
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PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
26
Figure 17-1. SPI Block Diagram
17.1
Operation as an SPI Master
Only an SPI Master can initiate a byte/data transfer. This is done by the Master writing to the SPI Data register. The Master shifts
out 8 bits of data (MSB first) along with the serial clock SCK for the Slave. The Master’s outgoing byte is replaced with an incoming
one from a Slave device. When the last bit is received, the shift register contents are transferred to the Receive Buffer and an
interrupt is generated. The receive data must be read from the SPI Data Register before the next byte of data is transferred to
the receive buffer, or the data will be lost.
When operating as a Master, an active LOW Slave Select (SS) must be generated to enable a Slave for a byte transfer. This Slave
Select is generated under firmware control, and is not part of the SPI internal hardware. Any available GPIO can be used for the
Master’s Slave Select output.
When the Master writes to the SPI Data Register, the data is loaded into the Transmit buffer. If the shift register is not busy shifting
a previous byte, the TX buffer contents will be automatically transferred into the shift register and shifting will begin. If the shift
register is busy, the new byte will be loaded into the shift register only after the active byte has finished and is transferred to the
Receive Buffer. The new byte will then be shifted out. The Transmit Buffer Full (TBF) bit will be set HIGH until the transmit buffer’s
data-byte is transferred to the shift register. Writing to the transmit buffer while the TBF bit is HIGH will overwrite the old byte in
the Transmit Buffer.
The byte shifting and SCK generation are handled by the hardware (based on firmware selection of the clock source). Data is
shifted out on the MOSI pin (P0.5) and the serial clock is output on the SCK pin (P0.7). Data is received from the slave on the
MISO pin (P0.6). The output pins must be set to the desired drive strength, and the GPIO data register must be set to 1 to enable
a bypass mode for these pins. The MISO pin must be configured in the desired GPIO input mode. See Section 12.0 for GPIO
configuration details.
17.2
Master SCK Selection
The Master’s SCK is programmable to one of four clock settings, as shown in Figure 17-1. The frequency is selected with the
Clock Select Bits of the SPI control register. The hardware provides 8 output clocks on the SCK pin (P0.7) for each byte transfer.
Clock phase and polarity are selected by the CPHA and CPOL control bits (see Figures 17-1 and 17-4).
The master SCK duty cycle is nominally 33% in the fastest (2 Mb/s) mode, and 50% in all other modes.
7
6
5
4
3
2
1
0
R/W
Data I/O [7]
Data I/O [6]
Data I/O [5]
Data I/O [4]
Data I/O [3]
Data I/O [2]
Data I/O [1]
Data I/O [0]
Figure 17-2. SPI Data Register (Address 0x60)
8 bit shift register
Data Bus
MOSI
MISO
SCK
SS
Master
/ Slave
Control
Write
Read
4
TX Buffer
RX Buffer
Internal SCK
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