參數(shù)資料
型號(hào)： CY7C63742-SC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24
封裝： 0.300 INCH, PLASTIC, SOIC-24
文件頁數(shù)： 25/48頁
文件大?。?/td> 425K
代理商： CY7C63742-SC
PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
31
By default, a capture timer register holds the time of the most recent edge for that register (i.e. if multiple edges have occurred
before reading the capture timer, the time for the last one will be read). Setting the global First Edge Hold (bit 7, Figure 19-6)
modifies this so that the first occurrence of an edge is held in the capture register until the data is read. In this case, subsequent
edges are ignored until the capture register is read. The First Edge Hold function applies globally to all four capture timers.
7
6
5
4
3
2
1
0
R
Capture A
Rising
Bit 7
Capture A
Rising
Bit 6
Capture A
Rising
Bit 5
Capture A
Rising
Bit 4
Capture A
Rising
Bit 3
Capture A
Rising
Bit 2
Capture A
Rising
Bit 1
Capture A
Rising
Bit 0
Figure 19-2. Capture Timer A-Rising, Data Register (Address 0x40)
7
6
5
4
3
2
1
0
R
Capture A
Falling
Bit 7
Capture A
Falling
Bit 6
Capture A
Falling
Bit 5
Capture A
Falling
Bit 4
Capture A
Falling
Bit 3
Capture A
Falling
Bit 2
Capture A
Falling
Bit 1
Capture A
Falling
Bit 0
Figure 19-3. Capture Timer A-Falling, Data Register (Address 0x41)
7
6
5
4
3
2
1
0
R
Capture B
Rising
Bit 7
Capture B
Rising
Bit 6
Capture B
Rising
Bit 5
Capture B
Rising
Bit 4
Capture B
Rising
Bit 3
Capture B
Rising
Bit 2
Capture B
Rising
Bit 1
Capture B
Rising
Bit 0
Figure 19-4. Capture Timer B-Rising, Data Register (Address 0x42)
7
6
5
4
3
2
1
0
R
Capture B
Falling
Bit 7
Capture B
Falling
Bit 6
Capture B
Falling
Bit 5
Capture B
Falling
Bit 4
Capture B
Falling
Bit 3
Capture B
Falling
Bit 2
Capture B
Falling
Bit 1
Capture B
Falling
Bit 0
Figure 19-5. Capture Timer B-Falling, Data Register (Address 0x43)
7
6
5
4
3
2
1
0
R/W
First Edge
Hold
Prescale
Bit 2
Prescale
Bit 1
Prescale
Bit 0
Capture B
Falling
Int Enable
Capture B
Rising
Int Enable
Capture A
Falling
Int Enable
Capture A
Rising
Int Enable
Figure 19-6. Capture Timers Configuration Register (Address 0x44)
7
6
5
4
3
2
1
0
-
R
Reserved
Capture B
Falling
Event
Capture B
Rising
Event
Capture A
Falling
Event
Capture A
Rising
Event
Figure 19-7. Capture Timers Status Register (Address 0x45)
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