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參數(shù)資料
| 型號： | CY7C63742-SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 425K |
| 代理商： | CY7C63742-SC |
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PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
21
13.1
USB Enumeration
A typical USB enumeration sequence is shown below. In this description, ‘Firmware’ refers to embedded firmware in the
CY7C637xx controller.
1. The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor.
2. Firmware decodes the request and retrieves its Device descriptor from the program memory tables.
3. The host computer performs a control read sequence and Firmware responds by sending the Device descriptor over the USB
bus, via the on-chip FIFO.
4. After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB
address to the device.
5. Firmware stores the new address in its USB Device Address Register after the no-data control sequence completes.
6. The host sends a request for the Device descriptor using the new USB address.
7. Firmware decodes the request and retrieves the Device descriptor from program memory tables.
8. The host performs a control read sequence and Firmware responds by sending its Device descriptor over the USB bus.
9. The host generates control reads from the device to request the Configuration and Report descriptors.
10.Once the device receives a Set Configuration request, its functions may now be used.
11.Firmware should take appropriate action for Endpoint 1 and/or 2 transactions, which may occur from this point.
13.2
USB Port Status and Control
USB status and control is regulated by the USB Status and Control Register as shown in Figure 13-1. All reserved bits must be
written to zero. All bits in the register are cleared during reset.
The Control Bits (bits 2:0) allow firmware to directly drive the D+ and D– pins, as shown in Table 13-1. Outputs are driven with
controlled edge rates in these modes for low EMI. For forcing these pins in USB mode (e.g. Force K for resume), Control Bit 2
should be 0. Setting Control Bit 2 HIGH puts both pins in an open-drain mode, preferred for applications such as PS/2 or LED
driving.
The Bus Activity bit (bit 3) is a “sticky” bit that indicates if any non-idle USB event has occurred on the USB bus. The user firmware
should check and clear this bit periodically to detect any loss of bus activity. Writing a “0” to the Bus Activity bit clears it while
writing a “1” preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it.
The 1.024-ms timer interrupt service routine is normally used to check and clear the Bus Activity bit.
Bits 4 is reserved and must be written as a 0.
The USB-PS/2 Interrupt Mode (bit 5) selects the definition of the USB Reset / PS/2 Activity Interrupt. The default cleared state
puts the interrupt into USB mode. Setting this bit HIGH switches the interrupt definition to PS/2 mode. Details of the mode
definitions are given in Section 21.3.1.
VREG Enable (bit 6) enables the 3.3V output voltage on the VREG pin when set to 1. This output is provided to source current
for a 1.5-k
pull-up resistor connected to the D– pin. On reset, this bit is cleared, so the VREG pin is in high-impedance state.
PS/2 Pullup Enable (bit 7) can be set to enable the internal PS/2 pull-up resistors on the SDATA and SCLK pins. Normally the
output high level on these pins is VCC, but note that the output will be clamped to approximately 1 Volt above VREG if the VREG
Enable bit is set, or if the Device Address is enabled (bit 7 of the USB Device Address Register, Figure 14-1).
7
6
5
4
3
2
1
0
R/W
-
R/W
PS/2 Pull-up
Enable
VREG
Enable
USB Reset-
PS/2 Activity
Interrupt
Mode
Reserved
USB
Bus Activity
Control
Bit 2
Control
Bit 1
Control
Bit 0
Figure 13-1. USB Status and Control Register (Address 0x1F)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C63743C-PXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-QXC | 功能描述:輸入/輸出控制器接口集成電路 LO Speed 3 Endpoint USB COM RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXCT | 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743-PC | 功能描述:IC MCU 8K LS USB/PS-2 24-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應用 系列:enCoRe™ 產品變化通告:Product Discontinuation 26/Aug/2009 標準包裝:250 系列:- 應用:網絡處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應商設備封裝:PG-LQFP-208 其它名稱:SP000314382 |
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