參數(shù)資料
型號(hào)： CY7C63742-SC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24
封裝： 0.300 INCH, PLASTIC, SOIC-24
文件頁(yè)數(shù)： 36/48頁(yè)
文件大?。?/td> 425K
代理商： CY7C63742-SC
PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
41
24.0
DC Characteristics
FOSC = 6 MHz; Operating Temperature = 0 to 70°C
Parameter
Min
Max
Units
Conditions
General
VCC1
Operating Voltage
4.0
5.5
V
Note 4
VCC2
Operating Voltage
4.35
5.25
V
Note 4
ICC
VCC Operating Supply Current
25
mA
VCC = 5.5V, no GPIO loading
ISB1
Standby Current - No Wake-up Osc
25
A
Oscillator off, D– > 2.8V
ISB2
Standby Current - With Wake-up Osc
75
A
Oscillator off, D– > 2.8V
VPP
Programming Voltage (disabled)
–0.4
0.4
V
TRSNTR
Resonator Start-up Interval
256
sV
CC = 5.0V, ceramic resonator
IIL
Input Leakage Current
1
AAny I/O pin
ISNK
Max ISS GPIO Sink Current
70
mA
Cumulative across all ports
[5]
ISRC
Max ICC GPIO Source Current
30
mA
Cumulative across all ports
[5]
Low Voltage & Power-On Reset
VLVR
Low-Voltage Reset Trip Voltage
3.6
3.9
V
VCC below VLVR for >100 ns
[6]
tVCCS
VCC Power-on Slew Time
100
ms
linear ramp: 0 to 4V
[7]
USB Interface
VRG
VREG Regulator Output Voltage
3.0
3.6
V
Load = RPU +RPD
[8, 9]
CREG
Capacitance on VREG Pin
300
pF
External cap not required
VOHU
Static Output High, driven
2.8
3.6
V
RPD to Gnd
[4]
VOLU
Static Output Low
0.3
V
With RPU to VREG pin
VOHZ
Static Output High, idle or suspend
2.7
3.6
V
RPD connected D– to Gnd, RPU con-
nected D– to VREG pin
[4]
VDI
Differential Input Sensitivity
0.2
V
|(D+)–(D–)|
VCM
Differential Input Common Mode Range
0.8
2.5
V
VSE
Single Ended Receiver Threshold
0.8
2.0
V
CIN
Transceiver Capacitance
20
pF
ILO
Hi-Z State Data Line Leakage
–10
10
A0 V < V
in<3.3 V (D+ or D– pins)
RPU
External Bus Pull-up resistance (D–)
1.274
1.326
k
1.3 k
±2% to VREG[10]
RPD
External Bus Pull-down resistance
14.25
15.75
k
15 k
±5% to Gnd
PS/2 Interface
VOLP
Static Output Low
0.4
V
Isink = 5 mA, SDATA or SCLK pins
RPS2
Internal PS/2 Pull-up Resistance
3
7
k
SDATA, SCLK pins, PS/2 Enabled
General Purpose I/O Interface
RUP
Pull-up Resistance
8
24
k
VICR
Input Threshold Voltage, CMOS mode
40%
60%
VCC
Low to high edge, Port 0 or 1
VICF
Input Threshold Voltage, CMOS mode
35%
55%
VCC
High to low edge, Port 0 or 1
VHC
Input Hysteresis Voltage, CMOS mode
3%
10%
VCC
High to low edge, Port 0 or 1
VITTL
Input Threshold Voltage, TTL mode
0.8
2.0
V
Ports 0, 1, and 2
VOL1A
VOL1B
Output Low Voltage, high drive mode
0.8
0.4
V
IOL1 = 50 mA, Ports 0 or 1
[4]
IOL1 = 25 mA, Ports 0 or 1
[4]
VOL2
Output Low Voltage, medium drive mode
0.4
V
IOL2 = 8 mA, Ports 0 or 1
[4]
VOL3
Output Low Voltage, low drive mode
0.4
V
IOL3 = 2 mA, Ports 0 or 1
[4]
VOH
Output High Voltage, strong drive mode
VCC–2
V
Port 0 or 1, IOH = 2 mA
[4]
RXIN
Pull-down resistance, XTALIN pin
50
k
Internal Clock Mode only
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