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參數(shù)資料
| 型號(hào)： | CY7C63742-SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 11/48頁 |
| 文件大?。?/td> | 425K |
| 代理商： | CY7C63742-SC |
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PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
19
The driving state of each pin is determined by the value written to the pin’s Data Register and by two Mode bits for each pin.
Table 12-1 lists the configuration states based on these bits. The GPIO ports default on reset to all Data and Mode Registers
cleared, so the pins are all in a high-impedance state. The available GPIO modes are:
Mode 00
High-impedance mode.
Mode 01
Medium Drive CMOS Mode: 8 mA sink current / 2 mA source current.
Mode 10
Low Drive / Resistive Mode: 2 mA sink current / 14 k
pull-up resistor.
Mode 11
High Drive CMOS Mode. 50 mA sink current / 2 mA source current.
Note that open drain mode can be achieved by fixing the Data and Mode1 Registers low, and switching the Mode0 register.
Input thresholds are CMOS (centered around VCC/2), or TTL as shown in the table. Both input modes include hysteresis to
minimize noise sensitivity. In suspend mode, if a pin is used for a wake-up interrupt using an external R-C circuit, CMOS mode
is preferred for lowest power.
Note that reading the GPIO port returns a byte based on the actual voltage of each pin, and does not affect the port’s Data or
Mode Registers.
The Port 0 Data Register is shown in Figure 12-2, and the Port 1 Data Register is shown in Figure 12-3. The Mode0 and Mode1
bits for the two GPIO ports are given in Figure 12-4 through Figure 12-7.
Note:
1.
When performing a read of the Port 0 or Port 1 Data registers, above, only the status of the GPIO pins will be read. The registers content will NOT be read.
Table 12-1. Ports 0 and 1 Output Control Truth Table
Data Register
Mode1
Mode0
Output Drive Strength
Input Threshold
0
Hi-Z
CMOS
0
1
0 - Medium Sink
CMOS
0
1
0
0 - Low Sink
CMOS
0
1
0 - High (50 mA) Sink
CMOS
1
0
Hi-Z
TTL
1
0
1
1 Strong
CMOS
1
0
1 Resistive
CMOS
1
1 Strong
CMOS
7
6
5
4
3
2
1
0
R/W
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
Figure 12-2. Port 0 Data (Address 0x00)[1]
7
6
5
4
3
2
1
0
R/W
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Pins 7:2 only in CY7C63742/43
Pins 1:0 in all parts
Figure 12-3. Port 1 Data (Address 0x01)[1]
7
6
5
4
3
2
1
0
W
P0.7 Mode0
P0.6 Mode0
P0.5 Mode0
P0.4 Mode0
P0.3 Mode0
P0.2 Mode0
P0.1 Mode0
P0.0 Mode0
Figure 12-4. GPIO Port 0 Mode0 Register (Address 0x0A)
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