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參數(shù)資料
| 型號： | CY7C63742-SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 29/48頁 |
| 文件大?。?/td> | 425K |
| 代理商： | CY7C63742-SC |
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PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
35
21.2
Interrupt Latency
Interrupt latency can be calculated from the following equation:
Interrupt Latency =
(Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) +
(5 clock cycles for the JMP instruction)
For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine will execute a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt
is issued. With a 6 MHz external resonator, internal CPU clock speed is 12 MHz, so 20 clocks take 20 / 12 MHz = 1.67
s.
21.3
Interrupt Sources
The following sections provide details on the different types of interrupt sources.
21.3.1
USB Bus Reset or PS/2 Activity
The function of this interrupt is selectable between detection of either a USB bus reset condition, or PS/2 activity. The selection
is made with the USB–PS/2 Interrupt Mode bit in the USB Status and Control Register (Figure 13-1). In either case, the interrupt
will occur if the selected condition exists for 256
s, and may occur as early as 128 s.
A USB bus reset is indicated by a single ended zero (SE0) on the USB D+ and D– pins. The USB interrupt occurs when the SE0
condition ends. PS/2 activity is indicated by a continuous low on the SDATA pin. The PS/2 interrupt occurs as soon as the long
low state is detected.
21.3.2
Free Running Timer Interrupts
There are two periodic timer interrupts from the free-running timer: the 128-
s interrupt and the 1.024-ms interrupt (based on a
6-MHz clock). The user should disable both timer interrupts before going into the suspend mode to avoid possible conflicts
between servicing the timer interrupts first or the suspend request first when waking up.
21.3.3
USB Endpoint Interrupts
There are three USB endpoint interrupts, one per endpoint. A USB endpoint interrupt is generated after the USB host writes to
a USB endpoint FIFO or after the USB controller sends a packet to the USB host. The interrupt is generated on the last packet
of the transaction (e.g., on the host’s ACK during an IN, or on the device ACK during on OUT). If no ACK is received during an
IN transaction, no interrupt will be generated.
21.3.4
SPI Interrupt
The SPI interrupt occurs at the end of each SPI byte transaction, at the final clock edge, as shown in Figure 17-4. After the
interrupt, the received data byte can be read from the SPI Data Register, and the TCMP control bit will be high
21.3.5
Capture Timer Interrupts
There are two capture timer interrupts, one for each associated pin. Each of these interrupts occurs on an enabled edge of the
selected GPIO pin(s). For each pin, rising and/or falling edge capture interrupts can be in selected. Refer to Section 19.0. These
interrupts are independent of the GPIO interrupt, described in the next section.
21.3.6
GPIO Interrupt
Each GPIO pin can serve as an interrupt input. During a reset, GPIO interrupts are disabled by clearing all GPIO interrupt enable
registers. Writing a 1 to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin. These registers
are shown in Figure 21-4 for Port 0 and Figure 21-5 for Port 1. In addition to enabling the desired individual pins for interrupt, the
main GPIO interrupt must be enabled, as explained in Section 21.0.
The polarity that triggers an interrupt is controlled independently for each GPIO pin by the GPIO Interrupt Polarity Registers.
Setting a Polarity bit to “0” allows an interrupt on a falling GPIO edge, while setting a Polarity bit to “1” allows an interrupt on a
rising GPIO edge. The Polarity Registers reset to 0 and are shown in Figure 21-6 for Port 0 and Figure 21-7 for Port 1.
All of the GPIO pins share a single interrupt vector, which means the firmware will need to read the GPIO ports with enabled
interrupts to determine which pin or pins caused an interrupt.The GPIO interrupt structure is illustrated in Figure 21-8.
Note that if one port pin triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to
its inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. The CY7C637xx does not assign interrupt
priority to different port pins and the Port Interrupt Enable Registers are not affected by the interrupt acknowledge process.
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| CY7C63743C-PXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-QXC | 功能描述:輸入/輸出控制器接口集成電路 LO Speed 3 Endpoint USB COM RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-SXCT | 功能描述:輸入/輸出控制器接口集成電路 USB/PS/2 Combo LoSpd Peripheral Controlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743-PC | 功能描述:IC MCU 8K LS USB/PS-2 24-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器 - 特定應(yīng)用 系列:enCoRe™ 產(chǎn)品變化通告:Product Discontinuation 26/Aug/2009 標(biāo)準(zhǔn)包裝:250 系列:- 應(yīng)用:網(wǎng)絡(luò)處理器 核心處理器:4Kc 程序存儲器類型:- 控制器系列:- RAM 容量:16K x 8 接口:以太網(wǎng)，UART，USB 輸入/輸出數(shù):- 電源電壓:1.8V, 3.3V 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:208-LQFP 包裝:帶卷 (TR) 供應(yīng)商設(shè)備封裝:PG-LQFP-208 其它名稱:SP000314382 |
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