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參數(shù)資料
| 型號： | CY7C63742-SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 27/48頁 |
| 文件大小： | 425K |
| 代理商： | CY7C63742-SC |
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PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
33
21.0
Interrupts
Interrupts can be generated by the GPIO lines, the internal free-running timer, the SPI block, the capture timers, on various USB
events, PS/2 activity, or by the wake-up timer. All interrupts are maskable by the Global Interrupt Enable Register and the USB
End Point Interrupt Enable Register. Writing a 1 to a bit position enables the interrupt associated with that bit position. During a
reset, the contents of the interrupt enable registers are cleared, along with the Global Interrupt enable bit of the CPU, effectively
disabling all interrupts.
The interrupt controller contains a separate flip-flop for each interrupt. See Figure 21-3 for the logic block diagram of the interrupt
controller. When an interrupt is generated it is first registered as a pending interrupt. It will stay pending until it is serviced or a
reset occurs. A pending interrupt will only generate an interrupt request if it is enabled by the corresponding bit in the interrupt
enable registers. The highest priority interrupt request will be serviced following the completion of the currently executing instruc-
tion.
When servicing an interrupt, the hardware will first disable all interrupts by clearing the Global Interrupt Enable bit in the CPU
(the state of this bit can be read at Bit 2 of the Processor Status and Control Register). Next, the flip-flop of the current interrupt
is cleared. This is followed by an automatic CALL instruction to the ROM address associated with the interrupt being serviced
(i.e., the Interrupt Vector, see Section 21.1). The instruction in the interrupt table is typically a JMP instruction to the address of
the Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service routine by executing an EI instruc-
tion. Interrupts can be nested to a level limited only by the available stack space.
The Program Counter value as well as the Carry and Zero flags (CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction generated as part of the interrupt acknowledge process. The user firmware is responsible for insuring that the
processor state is preserved and restored during an interrupt. The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP A instruction should be used just before the RETI instruction to
restore the accumulator value. The program counter, CF and ZF are restored and interrupts are enabled when the RETI instruction
is executed.
The DI and EI instructions can be used to disable and enable interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exits the ISR. While the global interrupt enable bit is cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and Control Register).
7
6
5
4
3
2
1
0
R/W
Wake-up
Interrupt
Enable
GPIO
Interrupt
Enable
Capture
Timer B
Intr. Enable
Capture
Timer A
Intr. Enable
SPI
Interrupt
Enable
1.024 ms
Interrupt
Enable
128
s
Interrupt
Enable
USB Reset /
PS/2 Activity
Intr. Enable
Figure 21-1. Global Interrupt Enable Register 0x20h (read/write)
7
6
5
4
3
2
1
0
R/W
Reserved
EP2
Interrupt
Enable
EP1
Interrupt
Enable
EP0
Interrupt
Enable
Figure 21-2. USB End Point Interrupt Enable Register (Address 0x21)
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