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參數(shù)資料
| 型號： | CY7C63742-SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 26/48頁 |
| 文件大?。?/td> | 425K |
| 代理商： | CY7C63742-SC |
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PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
32
20.0
Processor Status and Control Register
The Run bit (bit 0) is manipulated by the HALT instruction. When Halt is executed, the processor clears the run bit and halts at
the end of the current instruction. The processor remains halted until a reset occurs (low-voltage, brown-out, or watch dog). This
bit should normally be written as a 1.
Bit 1 is a reserved bit that must be written as a 0.
The Interrupt Enable Sense (bit 2) shows whether interrupts are enabled or disabled. Firmware has no direct control over this bit
as writing a zero or one to this bit position will have no effect on interrupts. A ‘0’ indicates that interrupts are masked off and a ‘1’
indicates that the interrupts are enabled. This bit is further gated with the bit settings of the Global Interrupt Enable Register (0x20)
and USB Endpoint Interrupt Enable Register (0x21). Instructions DI, EI, and RETI manipulate the state of this bit.
Writing a 1 to the Suspend bit (bit 3) will halt the processor and cause the microcontroller to enter the suspend mode that
significantly reduces power consumption. A pending, enabled interrupt or USB bus activity will cause the device to come out of
suspend. After coming out of suspend, the device will resume firmware execution at the instruction following the IOWR which put
the part into suspend. When writing the suspend bit with a resume condition present (such as non-idle USB activity), the suspend
state will still be entered, followed immediately by the wake-up process (with appropriate delays for the clock start-up). See Section
11.0 for more details on suspend mode operation.
The Low-Voltage or Brown-Out Reset (bit 4) is set to 1 during a power-on reset. Firmware can check bits 4 and 6 in the reset
handler to determine whether a reset was caused by a LVR/BOR condition or a watch dog timeout. (Note that a LVR/BOR event
may be followed by a watch dog reset before firmware begins executing, as explained below.)
The Bus Interrupt Event (bit 5) is set whenever the event for the USB Bus Reset / PS/2 Activity interrupt occurs. The event type
(USB or PS/2) is selected by the state of the USB-PS/2 Interrupt Mode bit (see Figure 13-1). The details on the event conditions
that set this bit are given in Section 21.3.1. In either mode, this bit is set as soon as the event has lasted for the specified time
(128–256
s), and the bit will be set even if the interrupt is not enabled. The bit is only cleared by firmware or LVR/WDR.
The Watch Dog Reset (bit 6) is set during a reset initiated by the Watch Dog Timer. This indicates the Watch Dog Timer went for
more than tWATCH (8 ms minimum) between Watch Dog clears. This can occur with a POR/LVR event, as noted below.
IRQ pending (bit 7), when set, indicates one or more of the interrupts has been recognized as active. This bit is only valid if the
Global Interrupt Enable bit is disabled. An interrupt will remain pending until its interrupt enable bit is set (registers 0x20 or 0x21)
and interrupts are globally enabled. At that point the internal interrupt handling sequence will clear this bit until another interrupt
is detected as pending.
During power-up, or during a low-voltage reset, the Processor Status and Control Register is set to 00010001, which indicates a
LVR/BOR (bit 4 set) has occurred and no interrupts are pending (bit 7 clear). Note that during the tSTART ms partial suspend at
start-up (explained in Section 10.1), a Watch Dog Reset will also occur. When a WDR occurs during the power-up suspend
interval, firmware would read 01010001 from the Status and Control Register after power-up. Normally the LVR/BOR bit should
be cleared so that a subsequent WDR can be clearly identified. Note that if a USB bus reset (long SE0) is received before firmware
examines this register, the Bus Interrupt Event bit would also be set.
During a Watch Dog Reset, the Processor Status and Control Register is set to 01XX0001, which indicates a Watch Dog Reset
(bit 4 set) has occurred and no interrupts are pending (bit 7 clear).
Table 19-1. Capture Timer Prescalar Settings (Step size and range for FCLK = 6 MHz)
Prescale 2:0
Capture From:
LSB Step Size
Range
000
Bits 7:0 of free running timer
1
s
256
s
001
Bits 8:1 of free running timer
2
s
512
s
010
Bits 9:2 of free running timer
4
s
1.024 ms
011
Bits 10:3 of free running timer
8
s
2.048 ms
100
Bits 11:4 of free running timer
16
s
4.096 ms
7
6
5
4
3
2
1
0
R
R/W
R
R/W
IRQ
Pending
Watch Dog
Reset
Bus Interrupt
Event
Low Voltage or
Brown-Out
Reset
Suspend
Interrupt
Enable
Sense
Reserved
Run
Figure 20-1. Processor Status and Control Register (Address 0xFF)
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