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參數(shù)資料
| 型號(hào)： | CY7C63742-SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 38/48頁 |
| 文件大?。?/td> | 425K |
| 代理商： | CY7C63742-SC |
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PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
43
Notes:
4.
Full functionality is guaranteed in VCC1 range, except USB transmitter specifications and GPIO output currents are guaranteed for VCC2 range.
5.
Total current cumulative across all Port pins, limited to minimize Power and Ground-Drop noise effects.
6.
LVR is automatically disabled during suspend mode.
7.
LVR will re-occur whenever VCC drops below VLVR. In suspend or with LVR disabled, BOR occurs whenever VCC drops below approximately 2.5V.
8.
VRG specified for regulator enabled, idle conditions (i.e. no USB traffic), with load resistors listed. During USB transmits from the internal SIE, the VREG output
is not regulated, and should not be used as a general source of regulated voltage in that case. During receive of USB data, the VREG output drops when D- is
low due to internal series resistance of approximately 200
at the VREG pin.
9.
In suspend mode, VRG is only valid if RPU is connected from D– to VREG pin, and RPD is connected from D– to ground.
10. The 200
internal resistance at the VREG pin gives a standard USB pull-up using this value. Alternately, a 1.5 k,5%pull-up from D- to an external 3.3V supply
can be used.
11. Initially FICLK2=FICLK until a USB packet is received.
12. Wake-up time for Wake-up Adjust Bits cleared to 000b (minimum setting)
13. Tested at 200 pF.
14. Measured at cross-over point of differential data signals.
15. Non-USB Mode refers to driving the D–/SDATA and/or D+/SCLK pins with the Control Bits of the USB Status and Control Register, with Control Bit 2 HIGH.
16. SPI timing specified for capacitive load of 50 pF, with GPIO output mode = 01 (medium low drive, strong high drive).
.
TMDO1
Master Data Output Time,
First bit with CPHA=1
100
ns
Time before leading SCK edge
TMSU
Master Input Data Set-Up time
50
ns
TMHD
Master Input Data Hold time
50
ns
TSSU
Slave Input Data Set-Up Time
50
ns
TSHD
Slave Input Data Hold Time
50
ns
TSDO
Slave Data Output Time
100
ns
SCK to data valid
TSDO1
Slave Data Output Time,
First bit with CPHA=1
100
ns
Time after SS LOW to data valid
TSSS
Slave Select Set-Up Time
150
ns
Before first SCK edge
TSSH
Slave Select Hold Time
150
ns
After last SCK edge
Figure 25-1. Clock Timing
Figure 25-2. USB Data Signal Timing
Parameter
Description
Min.
Max.
Unit
Conditions
CLOCK
TCYC
TCL
TCH
90%
10%
90%
10%
D
D
+
TR
TF
Vcrs
Voh
Vol
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