參數(shù)資料
型號(hào)： CY7C63742-SC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24
封裝： 0.300 INCH, PLASTIC, SOIC-24
文件頁(yè)數(shù)： 16/48頁(yè)
文件大?。?/td> 425K
代理商： CY7C63742-SC
PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
23
Bits[7:5] in the endpoint 0 mode registers are “sticky” status bits that are set by the SIE to report the type of token that was most
recently received by the corresponding device address. The sticky bits must be cleared by firmware as part of the USB processing.
The ACK bit (bit 4) is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet.
The SETUP PID status (bit 7) is forced HIGH from the start of the data packet phase of the SETUP transaction, until the start of
the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval, and subsequently until the
CPU first does a IORD to this endpoint 0 mode register.
Bits[6:0] of the endpoint 0 mode register are locked from CPU write operations whenever the SIE has updated one of these bits,
which the SIE does only at the end of a packet transaction (SETUP... Data... ACK, or OUT... Data... ACK, or IN... Data... ACK).
The CPU can unlock these bits by doing a subsequent read of this register.
Because of these hardware locking features, firmware must perform an IORD after an IOWR to an endpoint 0 register to verify
that the contents have changed as desired, and that the SIE has not updated these values.
While the SETUP bit is set, the CPU cannot write to the EP0 FIFO. This prevents firmware from overwriting an incoming SETUP
transaction before firmware has a chance to read the SETUP data.
The Mode bits (bits [3:0]) control how the endpoint responds to USB bus traffic. The mode bit encoding is shown in Table 22-1.
Additional information on the mode bits can be found in Table 22-2 and Table 22-3.
14.3
USB Non-Control Endpoints (2)
The format of the non-control endpoint mode registers is shown in Figure 14-3. EP1 uses an 8-byte FIFO at SRAM locations
0xF0–0xF7, while EP2 uses an 8-byte FIFO at SRAM locations 0xE8–0xEF, as shown in Section 8.2.
The Mode bits (bits [3:0]) of the Endpoint Mode Registers control how the endpoint responds to USB bus traffic. The mode bit
encoding is shown in Table 22-1.
The ACK bit (bit 4) is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet.
If STALL (bit 7) is set, the SIE will stall an OUT packet if the mode bits are set to ACK-IN, and the SIE will stall an IN packet if the
mode bits are set to ACK-OUT. For all other modes the STALL bit must be a LOW.
Bits 5 and 6 are reserved and must be written to zero during register writes.
14.4
USB Endpoint Counter Registers
There are three Endpoint Counter registers, with identical formats for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as bits for data packet status. The format of these registers is shown
in Figure 14-4.
The counter bits (bits [3:0]) indicate the number of data bytes in a transaction: For IN transactions, firmware loads the count with
the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8 inclusive. For OUT or SETUP
transactions, the count is updated by hardware to the number of data bytes received, plus 2 for the CRC bytes. Valid values are
2 to 10 inclusive.
Data Valid bit 6 is used for OUT and SETUP tokens only. Data is loaded into the FIFOs during the transaction, and then the Data
Valid bit will be set if a proper CRC is received. If the CRC is not correct, the endpoint interrupt will occur, but Data Valid will be
cleared to a zero.
Data 0/1 Toggle bit 7 selects the DATA packet’s toggle state: 0 for DATA0, 1 for DATA1. For IN transactions, firmware must set this
bit to the desired state. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit.
7
6
5
4
3
2
1
0
R/W
STALL
Reserved
ACK
Mode
Bit 3
Mode
Bit 2
Mode
Bit 1
Mode
Bit 0
Figure 14-3. USB Endpoint EP1, EP2 Mode Registers (Addresses 0x14, 0x16)
7
6
5
4
3
2
1
0
R/W
Data 0/1
Toggle
Data Valid
Reserved
Byte Count
Bit 3
Byte Count
Bit 2
Byte Count
Bit 1
Byte Count
Bit 0
Figure 14-4. USB Device Counter Registers (Addresses 0x11h, 0x13h, 0x15)
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