參數(shù)資料
型號(hào): CY7C63742-SC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24
封裝: 0.300 INCH, PLASTIC, SOIC-24
文件頁數(shù): 10/48頁
文件大?。?/td> 425K
代理商: CY7C63742-SC
PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
18
Once this timer is activated, it will give interrupts after its time-out period (see below). These interrupts continue periodically until
the interrupt is disabled. Whenever the interrupt is disabled, the wake-up timer is reset, so that a subsequent enable always results
in a full wake-up time.
The wake-up timer can be adjusted by the user through the Wake-up Timer Adjust bits in the Clock Configuration Register (Figure
9-2). These bits clear on reset. In addition to allowing the user to select a range for the wake-up time, a firmware algorithm can
be used to tune out initial process and operating condition variations in this wake-up time. This can be done by timing the wake-up
interrupt time with the accurate 1.024-ms timer interrupt, and adjusting the Timer Adjust bits accordingly to approximate the
desired wake-up time.
12.0
General Purpose I/O Ports
Ports 0 and 1 provide up to 16 versatile GPIO pins that can be read or written (the number of pins depends on package type).
Each pin can be configured as high-impedance inputs, inputs with internal pull-ups, open drain outputs, or traditional CMOS
outputs with selectable drive strengths. Figure 12-1 shows a diagram of a GPIO port pin. Each I/O pin can be configured
independently of any other pin. Port 0 is an 8-bit port; Port 1 contains either 2 bits, P1.1–P1.0 in the CY7C63722/23, or all 8-bits,
P1.7 - P1.0 in the CY7C63742/43 parts. Each bit can also be selected as an interrupt source for the microcontroller, as explained
in Section 21.3.6.
Figure 12-1. Block Diagram of GPIO Port (one pin shown)
Table 11-1. Wake-up Timer Adjust Settings
Adjust Bits [2:0]
(Bits [6:4] of Register 0xF8)
Wake-up Time
000 (reset state)
1 * tWAKE
001
2 * tWAKE
010
4 * tWAKE
011
8 * tWAKE
100
16 * tWAKE
101
32 * tWAKE
110
64 * tWAKE
111
128 * tWAKE
GPIO
Pin
VCC
14 k
GPIO
Mode
Data
Out
Register
Internal
Data Bus
Port Read
Port Write
Interrupt
Enable
Interrupt
C
ont
ro
l
To Interrupt
Controller
Q1
Q2
Q3
To Capture Timers (P0.0, P0.1)
and SPI (P0.4–P0.7))
Logic
Interrupt
Polarity
2
Threshold Select
SPI Bypass (P0.5–P0.7 only)
(=1 if SPI inactive, or for non-SPI pins)
(Data Reg must be 1
for SPI outputs)
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