參數(shù)資料
型號: CY7C63742-SC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24
封裝: 0.300 INCH, PLASTIC, SOIC-24
文件頁數(shù): 24/48頁
文件大?。?/td> 425K
代理商: CY7C63742-SC
PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
30
19.0
Timer Capture Registers
Four 8-bit timer capture registers provide both rising and falling edge event timing capture on two pins. Capture Timer A is
connected to Pin 0.0, and Capture Timer B is connected to Pin 0.1. These can be used to mark the time at which GPIO events
occur. Each timer will capture 8 bits of the free-running timer into a data register. A prescaler allows selection of the capture timer
tick size. Interrupts can be individually enabled for the four capture registers. A block diagram is shown in Figure 19-1.
Each of the four capture registers can be individually enabled to provide interrupts.
The four capture data registers are read-only, and are shown in Figure 19-2 through Figure 19-5.
Three prescaler bits allow the capture timer clock rate to be selected among 5 choices, as shown in Table 19-1 below. The Capture
Status Register (Figure 19-6) contains the prescale settings and the interrupt enables for the 4 possible events. Setting an enable
bit allows for an interrupt from the respective timer event. Note that both Capture A events share a common interrupt request, as
do the two Capture B events. In addition to the event enables, the main Capture Interrupt Enables in the Global Interrupt Enable
register (Section 21.0) must be set to activate a capture interrupt.
The Capture Status Register (Figure 19-7) records the occurrence of any rising or falling edges on the capture GPIO pins. Bits
in this register are cleared by reading the corresponding data register.
Figure 19-1. Capture Timers Block Diagram
Free-running Timer
GPIO
P0.0
11
10
9
8
7
4
3
2
1
0
1 MHz
Clock
Rising
Edge
Detect
Falling
Edge
Detect
Timer A Rising Edge Time
6
5
Timer A Falling Edge Time
Prescaler
GPIO
P0.1
Rising
Edge
Detect
Falling
Edge
Detect
Timer B Rising Edge Time
Timer B Falling Edge Time
8-bit Capture Registers
Capture Timer A Interrupt Request
Capture Timer B Interrupt Request
Capture B Falling Int Enable
Capture B Rising Int Enable
Capture A Falling Int Enable
Capture A Rising Int Enable
Bit 0, Reg 0x44
Bit 1, Reg 0x44
Bit 2, Reg 0x44
Bit 3, Reg 0x44
First Edge Hold
Bit 7, Reg 0x44
Mux
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