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參數(shù)資料
| 型號： | CY7C63742-SC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24 |
| 封裝： | 0.300 INCH, PLASTIC, SOIC-24 |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 425K |
| 代理商： | CY7C63742-SC |
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PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
15
9.1
Internal / External Oscillator Operation
The internal oscillator provides an operating clock, factory set to a nominal frequency of 6 MHz. This clock requires no external
components. At power-up, the chip operates from the internal clock. In this mode, the internal clock is buffered and driven to the
XTALOUT pin by default, and the state of the XTALIN Pin can be read at Port 2.1. While the internal clock is enabled, its output
can be disabled at the XTALOUT pin by setting the Internal Clock Output Disable bit of the Clock Configuration Register.
Setting bit 0 of the Clock Configuration Register disables the internal clock, and halts the part while the external resonator/crystal
oscillator is started. The steps involved in switching from Internal to External Clock mode are as follows:
1. At reset, chip begins operation using the internal clock.
2. Firmware sets Bit 0 of the Clock Configuration Register. For example,
mov A, 1h
; Set Bit 0 (External Oscillator Enable); bit 7 cleared gives faster start-up
iowr F8h
; Write to Clock Configuration Register
3. Internal clocking is halted, the internal oscillator is disabled, and the external clock oscillator is enabled.
4. After the external clock becomes stable, chip clocks are re-enabled using the external clock signal. (Note that the time for the
external clock to become stable depends on the external resonating device; see next section.)
5. After an additional delay the CPU is released to run. This delay depends on the state of the Ext. Clock Resume Delay bit of
the Clock Configuration Register. The time is 128
s if the bit is 0, or 4 ms if the bit is 1.
6. Once the chip has been set to external oscillator, it can only return to internal clock when waking from suspend mode. Clearing
bit 0 of the Clock Configuration Register will not re-enable internal clock mode until suspend mode is entered. See Section
11.0 for more details on suspend mode operation.
If the Internal Clock is enabled, the XTALIN pin can serve as a general purpose input, and its state can be read at Port 2, Bit 1
(P2.1). Refer to Figure 12-8 for the Port 2 data register. In this mode, there is a weak pull-down at the XTALIN pin. This input
cannot provide an interrupt source to the CPU.
9.2
External Oscillator
The user can connect a low-cost ceramic resonator or an external oscillator to the XTALIN / XTALOUT pins to provide a precise
reference frequency for the chip clock, as shown in Figure 9-1. The external components required are a ceramic resonator or
crystal with external capacitors. To run from the external resonator, Bit 0 of the Clock Configuration Register must be set to 1, as
explained in the previous section.
Start up times for the external oscillator depend on the resonating device. Ceramic resonator based oscillators typically start in
less than 100
s, while crystal based oscillators take longer, typically 1 to 10 ms. Board capacitance should be minimized on the
XTALIN and XTALOUT pins by keeping the traces as short as possible.
An external 6 MHz clock can be applied to the XTALIN pin if the XTALOUT pin is left open.
10.0
Reset
The USB Controller supports three types of resets. The effects of the reset are listed below. The reset types are:
1. Low Voltage Reset (LVR)
2. Brown Out Reset (BOR)
3. Watch Dog Reset (WDR)
The occurrence of a reset is recorded in the Processor Status and Control Register (see Figure 20-1). Bits 4 and 6 are used to
record the occurrence of LVR/BOR and WDR respectively. The firmware can interrogate these bits to determine the cause of a
reset.
The microcontroller begins execution from ROM address 0x0000 after a LVR, BOR or WDR reset. Although this looks like interrupt
vector 0, there is an important difference. Reset processing does NOT push the program counter, carry flag, and zero flag onto
program stack. Attempting to execute either a RET or RETI in the reset handler will cause unpredictable execution results.
The following events take place on reset. More details on the various resets are given in the following sections.
1. All registers are reset to their default states (all bits cleared, except in Processor Status and Control Register).
2. GPIO and USB pins are set to high-impedance state.
3. The VREG pin is set to high-impedance state.
4. Interrupts are disabled.
5. USB operation is disabled and must be enabled by firmware if desired, as explained in Section 14.1.
6. For a BOR or LVR, the external oscillator is disabled and Internal Clock mode is activated, followed by a time-out period tSTART
for VCC to stabilize. A WDR does not change the clock mode, and there is no delay for VCC stabilization on a WDR. Note that
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| CY7C63743C-PXC | 功能描述:輸入/輸出控制器接口集成電路 USB Combo Lo Spd PS/2 Periphrl Cntrlr RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CY7C63743C-QXC | 功能描述:輸入/輸出控制器接口集成電路 LO Speed 3 Endpoint USB COM RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
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