參數(shù)資料
型號： CY7C63742-SC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24
封裝： 0.300 INCH, PLASTIC, SOIC-24
文件頁數(shù)： 5/48頁
文件大?。?/td> 425K
代理商： CY7C63742-SC
PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
13
8.3
I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads the selected port into
the accumulator. IOWR writes data from the accumulator to the selected port. Indexed I/O Write (IOWX) adds the contents of X
to the address in the instruction to form the port address and writes data from the accumulator to the specified port. Note that
specifying address 0 with IOWX (e.g., IOWX 0h) means the I/O port is selected solely by the contents of X.
Note: All bits of all registers are cleared to all zeros on reset, except the Processor Status and Control Register (address
0xFF). All registers not listed are reserved, and should never be written by firmware. All bits marked as reserved should always
be written as 0.
Table 8-1. I/O Register Summary
Register Name
I/O Address
Read/Write
Function
Fig.
Port 0 Data
0x00
R/W
GPIO Port 0
12-2
Port 1 Data
0x01
R/W
GPIO Port 1
12-3
Port 2 Data
0x02
R
Auxiliary input register for D+, D–, VREG, XTALIN
12-8
Port 0 Interrupt Enable
0x04
W
Interrupt enable for pins in Port 0
21-4
Port 1 Interrupt Enable
0x05
W
Interrupt enable for pins in Port 1
21-5
Port 0 Interrupt Polarity
0x06
W
Interrupt polarity for pins in Port 0
21-6
Port 1 Interrupt Polarity
0x07
W
Interrupt polarity for pins in Port 1
21-7
Port 0 Mode0
0x0A
W
Controls output configuration for Port 0
12-4
Port 0 Mode1
0x0B
W
12-5
Port 1 Mode0
0x0C
W
Controls output configuration for Port 1
12-6
Port 1 Mode1
0x0D
W
12-7
USB Device Address
0x10
R/W
USB Device Address register
14-1
EP0 Counter Register
0x11
R/W
USB Endpoint 0 counter register
14-4
EP0 Mode Register
0x12
R/W
USB Endpoint 0 configuration register
14-2
EP1 Counter Register
0x13
R/W
USB Endpoint 1 counter register
14-4
EP1 Mode Register
0x14
R/W
USB Endpoint 1 configuration register
14-3
EP2 Counter Register
0x15
R/W
USB Endpoint 2 counter register
14-4
EP2 Mode Register
0x16
R/W
USB Endpoint 2 configuration register
14-3
USB Status & Control
0x1F
R/W
USB status and control register
13-1
Global Interrupt Enable
0x20
R/W
Global interrupt enable register
21-1
Endpoint Interrupt Enable
0x21
R/W
USB endpoint interrupt enables
21-2
Timer (LSB)
0x24
R
Lower 8 bits of free-running timer (1 MHz)
18-1
Timer (MSB)
0x25
R
Upper 4 bits of free-running timer
18-2
WDR Clear
0x26
W
Watch Dog Reset clear
-
Capture Timer A Rising
0x40
R
Rising edge Capture Timer A data register
19-2
Capture Timer A Falling
0x41
R
Falling edge Capture Timer A data register
19-3
Capture Timer B Rising
0x42
R
Rising edge Capture Timer B data register
19-4
Capture Timer B Falling
0x43
R
Falling edge Capture Timer B data register
19-5
Capture TImer Configuration
0x44
R/W
Capture Timer configuration register
19-6
Capture Timer Status
0x45
R
Capture Timer status register
19-7
SPI Data
0x60
R/W
SPI read and write data register
17-2
SPI Control
0x61
R/W
SPI status and control register
17-3
Clock Configuration
0xF8
R/W
Internal / External Clock configuration register
9-2
Processor Status & Control
0xFF
R/W
Processor status and control
20-1
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