參數(shù)資料
型號(hào)： CY7C63742-SC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24
封裝： 0.300 INCH, PLASTIC, SOIC-24
文件頁(yè)數(shù)： 15/48頁(yè)
文件大?。?/td> 425K
代理商： CY7C63742-SC
PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
22
14.0
USB Device
The CY7C637xx supports one USB Device Address with three endpoints: EP0, EP1, and EP2. Control Endpoint 0 (EP0) allows
the USB host to recognize, set-up, and control the device. In particular, EP0 is used to receive and transmit control (including
set-up) packets.
14.1
USB Address Register
The USB Device Address Register contains a 7-bit USB address and one bit to enable USB communication. This register is
cleared during a reset, setting the USB device address to zero and marking this address as disabled. Figure 14-1 shows the
format of the USB Address Register.
Bit 7 (Device Address Enable) in the USB Device Address Register must be set by firmware before the serial interface engine
(SIE) will respond to USB traffic at this address. The Device Address in bits [6:0] must be set by firmware during the USB enu-
meration process to the non-zero address assigned by the USB host. This register is cleared by both hardware resets and the
USB bus reset.
14.2
USB Control Endpoint
All USB devices are required to have an endpoint number 0 (EP0) that is used to initialize and control the USB device. EP0
provides access to the device configuration information and allows generic USB status and control accesses. EP0 is bidirectional
as the device can both receive and transmit data. EP0 uses an 8-byte FIFO at SRAM locations 0xF8–0xFF, as shown in Section
8.2.
The endpoint mode registers are cleared during reset. The EP0 endpoint mode register uses the format shown in Figure 14-2.
Table 13-1. Control Modes to Force D+/D– Outputs
Control Bits [2:0]
Control action
Application
000
Not forcing (SIE controls driver)
Any Mode
001
Force K (D+ HIGH, D– LOW)
USB Mode
010
Force J (D+ LOW, D– HIGH)
011
Force SE0 (D– LOW, D+ LOW)
100
Force D– LOW, D+ LOW
PS/2 Mode
[2]
101
Force D– LOW, D+ HiZ
110
Force D– HiZ, D+ LOW
111
Force D– HiZ, D+ HiZ
Note:
2.
For PS/2 operation, the [2:0] = 111b mode must be set initially (one time only) before using the other PS/2 force modes.
7
6
5
4
3
2
1
0
R/W
Device
Address
Enable
Device
Address
Bit 6
Device
Address
Bit 5
Device
Address
Bit 4
Device
Address
Bit 3
Device
Address
Bit 2
Device
Address
Bit 1
Device
Address
Bit 0
Figure 14-1. USB Device Address Register (Address 0x10)
7
6
5
4
3
2
1
0
R/W
Endpoint 0
SETUP
Received
Endpoint 0
IN
Received
Endpoint 0
OUT
Received
ACK
Mode
Bit 3
Mode
Bit 2
Mode
Bit 1
Mode
Bit 0
Figure 14-2. USB EP0 Mode Register (Address 0x12)
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