參數(shù)資料
型號： CY7C63742-SC
廠商： CYPRESS SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24
封裝： 0.300 INCH, PLASTIC, SOIC-24
文件頁數(shù)： 32/48頁
文件大?。?/td> 425K
代理商： CY7C63742-SC
PRELIMINARY
FO R
enCoRe USB CY7C63722/23
CY7C63742/43
38
The response of the SIE can be summarized as follows:
1. The SIE will only respond to valid transactions, and will ignore non-valid ones.
2. The SIE will generate an interrupt when a valid transaction is completed or when the FIFO is corrupted. FIFO corruption occurs
during an OUT or SETUP transaction to a valid internal address, that ends with a non-valid CRC.
3. An incoming Data packet is valid if the count is < Endpoint Size + 2 (includes CRC) and passes all error checking;
4. An IN will be ignored by an OUT configured endpoint and visa versa.
5. The IN and OUT PID status is updated at the end of a transaction.
6. The SETUP PID status is updated at the beginning of the Data packet phase.
7. The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that
endpoint in which an ACK is transferred. These registers are only unlocked by a CPU read of these registers, and only if that
read happens after the transaction completes. This represents about a 1-
s window in which the CPU is locked from register
writes to these USB registers. Normally the firmware should perform a register read at the beginning of the Endpoint ISRs to
unlock and get the mode register information. The interlock on the Mode and Count registers ensures that the firmware
recognizes the changes that the SIE might have made during the previous transaction.
Table 22-2. Decode table for Table 22-3: “Details of Modes for Differing Traffic Conditions”
Properties of incoming packet
Encoding
Status bits
What the SIE does to Mode bits
PID Status bits
Interrupt?
End Point Mode
End Point
Mode
3
2
1
0
Token
count
buffer
dval
DTOG
DVAL
COUNT
Setup
In
Out
ACK
3
2
1
0
Response
Int
Setup
In
Out
The validity of the received data
The quality status of the DMA buffer
The number of received bytes
Acknowledge phase completed
Legend:
UC: unchanged
TX: transmit
TX0: transmit 0-length packet
x: don’t care
RX: receive
available for Control endpoint only
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