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參數(shù)資料
| 型號： | CL-PD6710 |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 總線控制器 |
| 英文描述： | ISA-TOOPC-CARD HOST ADAPTERS |
| 中文描述： | PCMCIA BUS CONTROLLER, PQFP144 |
| 封裝： | VQFP-144 |
| 文件頁數(shù)： | 98/128頁 |
| 文件大?。?/td> | 1591K |
| 代理商： | CL-PD6710 |
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PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
98
ELECTRICAL SPECIFICATIONS
15.3.6
PC Card Bus Timing Calculations
Calculations for minimum PC Card cycle Setup, Command, and Recovery timings are made by first cal-
culating factors derived from the applicable timer set’s timing registers and then by applying the factor to
an equation relating it to the internal clock period.
The PC Card cycle timing factors, in terms of the number of internal clocks, are calculated as follows:
S
= (
N
pres
×
N
val
) + 1
Equation 15-1
C
= (
N
pres
×
N
val
) + 1
Equation 15-2
R
= (
N
pres
×
N
val
) + 1
Equation 15-3
N
pres
and N
val
are the specific selected prescaler and multiplier value from the timer set’s Setup, Com-
mand, and Recovery Timing registers (see
Chapter 10
for a description of these registers).
From this, a PC Card cycle’s Setup, Command, and Recovery time for the selected timer set are calcu-
lated as follows:
Setup time = (
S
×
Tcp
)
±
10 ns
Equation 15-4
Command time = (
C
×
Tcp
)
±
10 ns
Equation 15-5
Recovery time = (
R
×
Tcp
)
±
10 ns
Equation 15-6
When the internal synthesizer is used, the calculation of the internal clock period Tcpis:
Tcp
=
T
CLKP
×
4/7
Equation 15-7
where T
CLKP
is the period of the clock supplied to the CLK input pin. An input frequency of 14.318 MHz
at the CLK input pin results in an internal clock period of Tcp= 40 ns.
When the internal synthesizer is bypassed, Tcp= T
CLKP
. An input frequency of 25 MHz in this circum-
stance would also result in an internal clock period of Tcp= 40 ns.
The timing diagrams that follow were derived for a CL-PD67XX using the internal synthesizer and a
14.318-MHz CLK pin input. The internal clock frequency of the CL-PD67XX is 7/4 of this incoming signal
(Tcp= 40 ns). The examples are for the default values of the Timing registers for Timer Set 0, as follows:
Thus the minimum times for the default values are as follows:
Default minimum Setup time = (
S
×
Tcp
) – 10 ns = {2
×
40 ns} – 10 ns = 70 ns
Equation 15-8
Timing Register Name
(Timer Set 0)
Index
Value
(Default)
Resultant
N
pres
1
1
1
Resultant
N
val
1
6
3
Setup Timing 0
Command Timing 0
Recovery Timing 0
3Ah
3Bh
3Ch
01h
06h
03h
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PD6722 | ISA-TOOPC-CARD HOST ADAPTERS |
| CL-PS6700 | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS6700-VC-A | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS7110-VC-A | Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | Low-Power System-on-a-Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLPD6710VCB | 制造商:CIRRUS 功能描述:* |
| CL-PD6710-VC-B | 制造商:Cirrus Logic 功能描述:PCMCIA BUS CONTROLLER, PQFP144 |
| CLPD6720QCB | 制造商:CIRRUS 功能描述:* |
| CL-PD6720-QC-B | 制造商: 功能描述: |
| CL-PD6720QC-B | 制造商:CIRR 功能描述:6720-QC-B 制造商:Cirrus Logic 功能描述:6720-QC-B |
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