
PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
58
EXTENSION REGISTERS
9.
EXTENSION REGISTERS
9.1
Misc Control 1
Bit 0 — 5 V Detect (CL-PD6710 only)
This bit is connected to pins VS1 and VS2. Cards that will only operate at 3.3 V will drive this bit
to ‘0’.
Bit 1 — V
CC
3.3V
This bit determines which output pin is to be used to enable V
CC
power to the socket when card
power is to be applied; it is used in conjunction with bits 5:4 of the
Power Control
register (see
page 40
).
Bit 2 — Pulse Management Interrupt
This bit selects Level or Pulse mode operation of the IRQ[XX] or -INTR pin being used for card
status change management interrupts (see
page 14
). Note that a clock must be present on the
incoming CLK for pulsed interrupts to work.
a
On some versions of the CL-PD6722, this bit can be used to read levels of the A_GPSTB and B_GPSTB pins. Contact Cirrus
Logic for more information.
Register Name:
Misc Control 1
Index:
16h
Bit
7
Register Per: socket
Register Compatibility Type: ext.
Bit
1
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
Inpack Enable
Scratchpad Bits
Speaker
Enable
Pulse System
IRQ
Pulse
Management
Interrupt
V
CC
3.3V
5 V Detect
(CL-PD6710)
Reserved
a
(CL-PD6722)
R:X W:0
RW:0
RW:00
RW:0
RW:0
RW:0
RW:0
0
1
3.3 V card detected.
Old or 5 V card detected.
0
1
-VCC_5 activated when card power is to be applied.
-VCC_3 activated when card power is to be applied.
0
Card status change management interrupts are passed to the appropriate IRQ[XX] or -INTR pin as
level-sensitive.
When a card status change management interrupt occurs, the appropriate IRQ[XX] or -INTR pin is
driven with the pulse train shown in
Figure 9-1
and allows for interrupt sharing.
1