參數(shù)資料
型號(hào): CL-PD6710
廠商: CIRRUS LOGIC INC
元件分類: 總線控制器
英文描述: ISA-TOOPC-CARD HOST ADAPTERS
中文描述: PCMCIA BUS CONTROLLER, PQFP144
封裝: VQFP-144
文件頁數(shù): 68/128頁
文件大小: 1591K
代理商: CL-PD6710
PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
68
EXTENSION REGISTERS
Figure 9-2. Selection of Acknowledge Time-out Interval
The maximum DMA acknowledge delay (t2 as shown in
Figure 9-2
) should be programmed to a time
greater than the maximum time required from the system’s issuance of a DMA acknowledge to its issu-
ance of a DMA read or write cycle (t1 as shown in
Figure 9-2
). The t1 time is indicated in the specifications
for the systems DMA cycle timing.
Typical system specifications for t1 are 190–270 ns, making a value of 80h for the
Maximum DMA
Acknowledge Delay
register suitable for many applications. If the CL-PD6722 is used in an add-in card
application, a value of 20h may be suitable.
Table 9-1
shows
Maximum DMA Acknowledge Delay
reg-
ister values to be programmed for a desired maximum DMA acknowledge delay.
Table 9-1.
Maximum DMA Acknowledge Delay Register Values
Register Value
Maximum DMA Acknowledge Delay
(25-MHz internal clock and default Setup timing)
80h
40h
C0h
20h
A0h
60h
E0h
10h
90h
50h
D0h
30h
B0h
7 clocks = 280 ns
8 clocks = 320 ns
9 clocks = 360 ns
10 clocks = 400 ns
11 clocks = 440 ns
12 clocks = 480 ns
13 clocks = 520 ns
14 clocks = 560 ns
15 clocks = 600 ns
16 clocks = 640 ns
17 clocks = 680 ns
18 clocks = 720 ns
19 clocks = 760 ns
DREQ
DACK*
AEN
IOR*/IOW*
t2
t1
t1 = time delay from DMA acknowledge to IOR* or IOW* command (specified by system design).
t2 = time to program into the Maximum DMA Acknowledge Delay register for when IOR* or IOW* falling edge does not occur (t2 > t1).
相關(guān)PDF資料
PDF描述
CL-PD6722 ISA-TOOPC-CARD HOST ADAPTERS
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