
PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
126
INDEX
N
Normal Byte Read/Write timing
103
O
Odd Byte timing
104
-OE
16
Offset Address
15:8 bits
52
19:12 bits
56
25:20 bits
57
7:1 bits
52
ordering information
113
P
package
144-pin VQFP
110
208-pin PQFP
111
208-pin VQFP
112
PC Card
basics
22
bus timing calculations
98
Read/Write timing
102
socket timing
99
timing
29
PCMCIA
22
pin descriptions
8
,
20
pin diagram
144-pin VQFP
9
208-pin PQFP or VQFP
10
pin usage summary
21
power consumption
28
Power Control register
40
power management
27
power-on
configuration
21
setup
31
Pull-up Control bit
67
Pulse Management Interrupt bit
58
Pulse Mode Interrupt timing
95
Pulse System IRQ bit
59
PWRGOOD
12
R
RDY/-IREQ
17
Ready Change bit
44
Ready Enable bit
45
Ready/Busy* bit
39
Recovery Multiplier Value bits
74
Recovery Prescalar Select bits
74
Recovery Timing 0–1 registers
74
REFRESH*
12
-REG
16
REG Setting bit
57
Register Index bits
33
register summary tables
116
–
123
RESET
18
Reset timing
94
Revision bits
37
-RI
19
RI_OUT*
14
Ring Indicate Enable bit
43
S
SA[16:0]
12
SBHE*
12
SD[15:0]
12
Setup Multiplier Value bits
72
Setup Prescalar Select bit
72
Setup Timing 0–1 registers
72
SLOT_VCC. See SOCKET_VCC
socket
accessing specific registers
33
register per
32
Socket Index bit
33
socket interface pins
16
–
19
socket power features
28
SOCKET_VCC
19
Speaker Enable bit
59
Speaker Is LED Input bit
64
-SPKR
18
SPKR_OUT*/C_SEL
15
Start Address
15:8 bits
50
19:12 bits
53
23:20 bits
54
7:0 bits
50
-STSCHG
19
Super-Suspend mode, description
27
Suspend bit
61
Suspend mode, description
27
System I/O Map 0–1
End Address High registers
51
End Address Low registers
51
Start Address Low registers
50
System Interrupt timing
95
System Memory Map 0–4
End Address High registers
55
End Address Low registers
54
Start Address High registers
54
Start Address Low registers
53