參數(shù)資料
型號： CL-PD6710
廠商： CIRRUS LOGIC INC
元件分類： 總線控制器
英文描述： ISA-TOOPC-CARD HOST ADAPTERS
中文描述： PCMCIA BUS CONTROLLER, PQFP144
封裝： VQFP-144
文件頁數(shù)： 92/128頁
文件大小： 1591K
代理商： CL-PD6710
PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
92
ELECTRICAL SPECIFICATIONS
15.3.1
ISA Bus Timing
Table 15-7. ISA Bus Timing
Symbol
Parameter
MIN
MAX
Unit
t
1
MEMCS16* active delay from LA[23:17] valid
40
ns
t
1a
LA[23:17] setup to ALE inactive
30
ns
t
1b
LA[23:17] hold from ALE inactive
5
ns
t
2
IOCS16* active delay from SA[15:0]
1
40
ns
t
2a
IOCS16* inactive delay from SA[15:0]
1
40
ns
t
3
SA[16:0], SBHE* setup to any Command active
1, 2
LA[23:17] latching by ALE to any Command active
30
90
ns
ns
t
4
Any Command active to IOCHRDY inactive (low)
3
40
ns
t
4a
IOCHRDY three-state from Command inactive
4
5
30
t
5
MEMCS16* inactive delay from unlatched LA[23:17]
40
ns
t
6a
IOW* or IOR* pulse width
1
140
ns
t
6b
MEMW* or MEMR* pulse width
1
180
ns
t
7
Any Command inactive to next Command active
100
ns
t
8
Address or SBHE* hold from any Command inactive
0
ns
t
9
Data valid from MEMW* active
5
Data valid from IOW* active
40
40
ns
ns
t
10
Data hold from MEMW* inactive
Data hold from IOW* inactive
5
5
ns
ns
t
11
Data delay from IOR* active, for internal registers
0
130
ns
t
12
Data delay from IOCHRDY active
15
ns
t
13
Data hold from IOR* or MEMR* inactive
0
30
ns
t
14
AEN inactive setup to valid IOR* or IOW* active
40
ns
t
15
AEN hold from IOR* or IOW* inactive
5
ns
t
16
REFRESH* inactive setup to valid MEMR* or MEMW* active
40
ns
t
17
REFRESH* inactive hold from MEMR* or MEMW* active
0
ns
t
18
MEMCS16* active delay from SA[16:12] valid
40
ns
t
19
*ZWS delay from MEMW* active
30
ns
t
20
*ZWS hold from MEMW* inactive
15
ns
1
2
3
4
5
AEN must be inactive for t
2
, t
3
, and t
6
timing specifications to be applicable.
Command is defined as IOR*, IOW*, MEMR*, or MEMW*.
Except for valid card memory writes, which are zero wait state when internal write FIFO is not full.
If card is removed during a card access cycle, IOCHRDY is three-stated without waiting for end of Command.
Based on 25-MHz internal clock, produced either by an internal synthesizer and 14.318-MHz signal applied to CLK pin,
or by supplying 25 MHz directly to CLK pin and bypassing the internal synthesizer.
相關(guān)PDF資料
PDF描述
CL-PD6722 ISA-TOOPC-CARD HOST ADAPTERS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CLPD6710VCB 制造商:CIRRUS 功能描述:*
CL-PD6710-VC-B 制造商:Cirrus Logic 功能描述:PCMCIA BUS CONTROLLER, PQFP144
CLPD6720QCB 制造商:CIRRUS 功能描述:*
CL-PD6720-QC-B 制造商: 功能描述:
CL-PD6720QC-B 制造商:CIRR 功能描述:6720-QC-B 制造商:Cirrus Logic 功能描述:6720-QC-B
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