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參數(shù)資料
| 型號(hào)： | CL-PD6710 |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 總線控制器 |
| 英文描述： | ISA-TOOPC-CARD HOST ADAPTERS |
| 中文描述： | PCMCIA BUS CONTROLLER, PQFP144 |
| 封裝： | VQFP-144 |
| 文件頁數(shù)： | 55/128頁 |
| 文件大?。?/td> | 1591K |
| 代理商： | CL-PD6710 |
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CL-PD6710/’22
ISA–to–PC-Card Host Adapters
May 1997
55
PRELIMINARY DATA SHEET v3.1
MEMORY WINDOW MAPPING REGISTERS
Bits 7:0 — End Address 19:12
This register contains the least-significant byte of the address that specifies where in the memory
space the corresponding memory map will end. Memory accesses that are equal or below this
address and equal or above the corresponding System Memory Map Start Address will be
mapped into the memory space of the corresponding PC Card.
The most-significant four bits are located in the
System Memory Map 0–4 End Address High
register (see
Section 8.4
).
8.4
System Memory Map 0–4 End Address High
There are five separate System Memory Map End Address High registers, each with identical fields.
These registers are located at the following indexes:
Index
13h
1Bh
23h
2Bh
33h
System Memory Map End Address High
System Memory Map 0 End Address High
System Memory Map 1 End Address High
System Memory Map 2 End Address High
System Memory Map 3 End Address High
System Memory Map 4 End Address High
Bits 3:0 — End Address 23:20
This field contains the most-significant four bits of the End Address. See the description of the End
Address field associated with bits 7:0 of the
System Memory Map 0–4 End Address Low
regis-
ter (see page
54
).
Bits 7:6 — Card Timer Select
This field selects the Timeset registers used to control socket timing for card accesses in this
window address range. Timeset 0 and 1 reset to values compatible with PC Card standards. The
mapping of bits 7:6 to Timeset 0 and 1, as shown in the preceding table, is done for software
compatibility with older ISA bus-based PCMCIA host adapters that use ISA bus wait states instead
of Timeset registers (see
page 72
).
Register Name:
System Memory Map 0–4 End Address High
Index:
13h, 1Bh, 23h, 2Bh, 33h
Bit
7
Bit
6
Register Per: socket
Register Compatibility Type: 365
Bit
1
Bit
5
Bit
4
Bit
3
Bit
2
Bit
0
Card Timer Select
Scratchpad Bits
End Address 23:20
RW:00
RW:00
RW:0000
00
Selects Timer Set 0.
01
Selects Timer Set 1.
10
Selects Timer Set 1.
11
Selects Timer Set 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL-PD6722 | ISA-TOOPC-CARD HOST ADAPTERS |
| CL-PS6700 | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS6700-VC-A | Low-Power PC Card Controller for the CL-PS7111 |
| CL-PS7110-VC-A | Low-Power System-on-a-Chip |
| CL-PS7110-VI-A | Low-Power System-on-a-Chip |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CLPD6710VCB | 制造商:CIRRUS 功能描述:* |
| CL-PD6710-VC-B | 制造商:Cirrus Logic 功能描述:PCMCIA BUS CONTROLLER, PQFP144 |
| CLPD6720QCB | 制造商:CIRRUS 功能描述:* |
| CL-PD6720-QC-B | 制造商: 功能描述: |
| CL-PD6720QC-B | 制造商:CIRR 功能描述:6720-QC-B 制造商:Cirrus Logic 功能描述:6720-QC-B |
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