
May 1997
3
PRELIMINARY DATA SHEET v3.1
CL-PD6710/’22
ISA–to–PC-Card Host Adapters
Table of Contents
1.
2.
2.1
2.2
2.3
2.4
3.
3.1
3.1.1
3.1.2
3.1.3
3.1.4
3.1.5
3.1.6
3.1.7
3.1.8
3.1.9
3.1.10 Write FIFO....................................................29
3.1.11 Bus Sizing.....................................................29
3.1.12 Programmable PC Card Timing....................29
3.1.13 ATA Mode Operation.....................................29
3.1.14 DMA Mode Operation for
the CL-PD6722.............................................30
3.1.15 Selective Data Drive for I/O Windows...........30
3.2
Host Access to Registers.................................30
3.3
Power-On Setup...............................................31
4.
REGISTER DESCRIPTION
CONVENTIONS................................... 32
5.
OPERATION REGISTERS.................. 33
5.1
Index................................................................33
5.2
Data .................................................................36
6.
CHIP CONTROL REGISTERS............ 37
6.1
Chip Revision...................................................37
6.2
Interface Status................................................38
6.3
Power Control ..................................................40
6.4
Interrupt and General Control..........................42
6.5
Card Status Change ........................................44
6.6
Management Interrupt Configuration...............45
6.7
Mapping Enable...............................................47
7.
I/O WINDOW MAPPING
REGISTERS ........................................ 49
7.1
I/O Window Control..........................................49
7.2
System I/O Map 0–1 Start Address Low..........50
7.3
System I/O Map 0–1 Start Address High.........50
7.4
System I/O Map 0–1 End Address Low...........51
7.5
System I/O Map 0–1 End Address High..........51
GENERAL CONVENTIONS.................. 7
PIN INFORMATION............................... 8
Pin Diagrams .....................................................9
Pin Description Conventions............................11
Pin Descriptions...............................................12
Power-On Configuration Summary..................21
INTRODUCTION.................................. 22
System Architecture.........................................22
PC Card Basics ............................................22
CL-PD67XX Windowing Capabilities............22
CL-PD67XX Functional Blocks.....................25
Interrupts ......................................................25
Alternate Functions of Interrupt Pins............26
General-Purpose Strobe Feature .................26
Voltage Sense Pins.......................................27
CL-PD67XX Power Management.................27
Socket Power Management Features...........28
7.6
7.7
8.
Card I/O Map 0–1 Offset Address Low............52
Card I/O Map 0–1 Offset Address High...........52
MEMORY WINDOW MAPPING
REGISTERS.........................................53
System Memory Map 0–4 Start Address
Low ..................................................................53
System Memory Map 0–4 Start Address
High..................................................................54
System Memory Map 0–4 End Address
Low ..................................................................54
System Memory Map 0–4 End Address
High..................................................................55
Card Memory Map 0–4 Offset Address
Low ..................................................................56
Card Memory Map 0–4 Offset Address
High..................................................................56
EXTENSION REGISTERS...................58
Misc Control 1..................................................58
FIFO Control....................................................60
Misc Control 2..................................................61
Chip Information...............................................63
ATA Control......................................................64
Extended Index................................................65
Extended Data.................................................65
Data Mask 0–1 .............................................66
Extension Control 1 (CL-PD6722 only,
formerly DMA Control)..................................66
Maximum DMA Acknowledge Delay
(CL-PD6722 only).........................................67
External Data (CL-PD6722 only, Socket A,
Index 2Fh).....................................................69
External Data (CL-PD6722 only, Socket A,
Index 6Fh).....................................................70
Extension Control 2 (CL-PD6722 only) ........71
10. TIMING REGISTERS ...........................72
10.1 Setup Timing 0–1.............................................72
10.2 Command Timing 0–1......................................73
10.3 Recovery Timing 0–1.......................................74
11. ATA MODE OPERATION.....................75
12. USING GPSTB PINS FOR EXTERNAL
PORT CONTROL (CL-PD6722 only)..77
12.1 Control of GPSTB Pins....................................77
12.2 Example Implementations of GPSTB-Controlled
Read and Write Ports.......................................79
12.3 GPSTB in Suspend Mode................................80
13. VS1# AND VS2# VOLTAGE
DETECTION.........................................81
8.1
8.2
8.3
8.4
8.5
8.6
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.7.2
9.7.3
9.7.4
9.7.5
9.7.6