參數(shù)資料
型號: celeron processor
廠商: Intel Corp.
英文描述: 32 bit Celeron Processor Mobile Module(32 位帶移動模塊處理器)
中文描述: 32位賽揚處理器的移動模塊(32位帶移動模塊處理器)
文件頁數(shù): 40/64頁
文件大小: 799K
代理商: CELERON PROCESSOR
Celeron
Processor Mobile Module MMC-2
at 650 MHz, 600 MHz, 550 MHz, 500 MHz, and 450 MHz
34
Datasheet
243357-004
6.
VR_ON must monotonically rise through its V
IL
to V
IH
and fall through its V
IH
to V
IL
points.
The sign of slope can not change between V
IL
and V
IH
in rising and V
IH
and V
IL
in falling.
7.
VR_ON must provide an instantaneous in-rush current to the mobile module with the
following values as listed in
Table 24
.
8.
VR_ON Valid-Low Time: This specifies how long VR_ON needs to be low for a valid off
before VR_ON can be turned back on again. In going from a valid on to off and then back on,
the following conditions must be met to prevent damage to the system or the mobile module:
VR_ON must be low for 1.0 mS
The original voltage level requirements for turn-on must be met before assertion of
VR_ON (i.e. V_DC
7.5V, V_5
4.5V, and V_3
3.0V)
Figure 6. Power Sequence Timing
Table 24. VR_ON In-rush Current
Instantaneous
DC Operating
Maximum
41.0 mA
0.1
μ
A
Typical
0.2 mA
0.0
μ
A
NOTES:
1. PW ROK on I/O board should be active on when VR_PW RGD is active and V_3S is good.
2. CPU_RST from I/O board should be active for a minimum of 6.0 mS after PW ROK is active and PLL_STP# and CPU_STP# are inactive.
Note that PLL_STP# is an AND condition of RSMRST# and SUSB# on the PIIX4E/M.
3. This is the 5V power supplied to the MMC-2 connector. This should be the first 5.0-V plane to power up. It stays on during suspend.
4. V_DC >= 7.5V, V_5>=4.5V, V_3S>=3.0V.
5. VR_PW RGD is specified active by the module regulator within less than or equal to 6.0-mS maximum after the assertion of VR_ON.
6. V_CPUPU and V_CLK are generated on the mobile module.
V_CPUPU
V_CLK
NOTE 6
NOTE 6
VR_PW RGD
V_DC
V_3
V_5
V_3S
VR_ON
NOTE 4
0 MS MIN
NOTE 3
0 MS MIN
NOTE 5
0 MS MIN
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