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| 型號： | celeron processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit Celeron Processor Mobile Module(32 位帶移動模塊處理器) |
| 中文描述： | 32位賽揚(yáng)處理器的移動模塊（32位帶移動模塊處理器） |
| 文件頁數(shù)： | 39/64頁 |
| 文件大小： | 799K |
| 代理商： | CELERON PROCESSOR |
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Celeron
Processor Mobile Module MMC-2
at 650 MHz, 600 MHz, 550 MHz, 500 MHz, and 450 MHz
243357-004
Datasheet
33
The following list includes additional specifications and clarifications of the power sequence
timing and
Figure 6
provides an illustration.
1.
The VR_ON signal may only be asserted to a logical high by a digital signal after V_DC
≥
7.5V, V_5
≥
4.5V, and V_3
≥
3.0V.
2.
The Rise Time and Fall Time of VR_ON must be less than or equal to 1.0
μ
S.
3.
VR_ON has its V
IL max
= +0.4V and V
IH min
= +3.0V.
4.
The VR_PWRGD will get asserted to logic high (3.3V) after V_CORE is stabilized and V_DC
reaches 7.5V. This signal should not and can not be pulled up by the system electronics.
5.
In the power-on process, Intel recommends to raise the higher voltage power plane first
(V_DC), followed by the lower power planes (V_5, V_3), and finally assert VR_ON after
above voltage levels are met on all rails. The power-off process should be the reverse process,
i.e. VR_ON gets deasserted, followed by the lower power planes, and finally the higher power
planes.
Table 23. Voltage Signal Definitions and Sequences
Signal
Source
Definition and Sequences
V_DC
System Electronics
V_DC is required to be between 7.5V and 21.0V DC and is driven by
the system electronics' power supply. V_DC powers the mobile
module DC-to-DC converter for the processor core and I/O voltages.
The mobile module cannot be hot inserted or removed while
V_DC is powered on.
V_5
System Electronics
V_5 is supplied by the system electronics for the voltage regulator.
V_3
System Electronics
V_3 is supplied by the system electronics for the 443BX and powers
the mobile module's linear regulators for generating the V_CLK and
V_CPUPU voltage rails. V_3 stays on during suspend.
V_3S
System Electronics
V_3S is supplied by the system electronics and is shut off during
suspend.
VR_ON
System Electronics
VR_ON is a 3.3-V signal that enables the voltage regulator circuit.
When driven active high the voltage regulator circuit is activated. The
signal driving VR_ON should be a digital signal with a rise/fall time of
less than or equal to 1.0
μ
S. (V
IL,max
=0.4V, V
IH,min
=3.0V.)
V_CORE
Module
A result of VR_ON being asserted, V_CORE is an output of the DC-
DC regulator on the mobile module and is driven to the core voltage of
the processor.
VR_PWRGD
Module
Upon sampling the voltage level of V_CORE (minus tolerances for
ripple), VR_PWRGD is driven active high. If VR_PWRGD is not
sampled active within 1 second of the assertion of VR_ON, then the
system electronics should deassert VR_ON. After V_CORE is
stabilized, VR_PWRGD will assert to logic high (3.3V). This signal
must not be pulled up by the system electronics. VR_PWRGD should
be "logically ANDed" with V_3S to generate the PIIX4E/M input signal,
PWROK. The system electronics should monitor VR_PWRGD to verify
it is asserted high prior to the active high assertion of PIIX4E/M
PWROK.
V_CPUPU
Module
V_CPUPU is 1.5V. The system electronics uses this voltage to power
the PIIX4E/M-to-processor interface circuitry.
V_CLK
Module
V_CLK is 2.5V. The system electronics uses this voltage to power the
HCLK[0:1] drivers for the processor clock.
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