參數(shù)資料
型號(hào)： celeron processor
廠商： Intel Corp.
英文描述： 32 bit Celeron Processor Mobile Module(32 位帶移動(dòng)模塊處理器)
中文描述： 32位賽揚(yáng)處理器的移動(dòng)模塊（32位帶移動(dòng)模塊處理器）
文件頁(yè)數(shù)： 18/64頁(yè)
文件大小： 799K
代理商： CELERON PROCESSOR
Celeron
Processor Mobile Module MMC-2
at 650 MHz, 600 MHz, 550 MHz, 500 MHz, and 450 MHz
12
Datasheet
243357-004
3.1.7
Clock Signals
Table 7
provides descriptions of the clock signals.
Table 7. Clock Signal Definitions
Name
Type
Voltage
Description
PCLK
I
PCI
V_3
PCI Clock In:
PCLK, an input to the mobile module, is one of the
system’s PCI clocks.
This clock is used by all of the 82443BX Host
Bridge logic in the PCI clock domain.
This clock is stopped when the
PIIX4E/M PCI_STP# signal is asserted and/or during all suspend
states.
HCLK0
I
CMOS
V_CLK
Host Clock In:
This clock is input to the mobile module from the
CK100-M/CK100-SM clock source. The processor and the 82443BX
Host Bridge system controller use HCLK0. This clock is stopped when
the PIIX4E/M CPU_STP# signal is asserted and/or during all suspend
states.
HCLK1
I
CMOS
V_CLK
Host Clock In:
This clock is an input to the mobile module from the
CK100-M/CK100-SM clock source.
This signal is not implemented on the mobile module
.
DCLK0
O
CMOS
V_3
SDRAM Clock Out:
A 66-MHz SDRAM clock reference generated
internally by the 82443BX Host Bridge system controller onboard PLL.
It feeds an external buffer that produces multiple copies for the SO-
DIMMs.
DCLKRD
I
CMOS
V_3
SDRAM Read Clock:
Feedback reference from the SDRAM clock
buffer. The 82443BX Host Bridge System Controller uses this clock
when reading data from the SDRAM array.
This signal is not implemented on the mobile module
.
DCLKWR
I
CMOS
V_3
SDRAM Write Clock:
Feedback reference from the SDRAM clock
buffer. The 82443BX Host Bridge system controller uses this clock
when writing data to the SDRAM array.
GCLKIN
I
CMOS
V_3
AGP Clock In:
The GCLKIN input is a feedback reference from the
GCLKO signal.
GCLKO
O
CMOS
V_3
AGP Clock Out:
This signal is generated by the 82443BX Host
Bridge system controller onboard the PLL from the HCLK0 host clock
reference. The frequency of GCLKO is 66 MHz. The GCLKO output is
used to feed both the PLL reference input pins on the 82443BX Host
Bridge system controller and the AGP device. The board layout must
maintain complete symmetry on loading and trace geometry to
minimize AGP clock skew.
FQS
O
CMOS
V_3S
Frequency Select:
This output indicates the desired host clock
frequency for the mobile module.
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