參數(shù)資料
型號(hào)： celeron processor
廠商： Intel Corp.
英文描述： 32 bit Celeron Processor Mobile Module(32 位帶移動(dòng)模塊處理器)
中文描述： 32位賽揚(yáng)處理器的移動(dòng)模塊（32位帶移動(dòng)模塊處理器）
文件頁(yè)數(shù)： 11/64頁(yè)
文件大?。?/td> 799K
代理商： CELERON PROCESSOR
Celeron
Processor Mobile Module MMC-2
at 650 MHz, 600 MHz, 550 MHz, 500 MHz, and 450 MHz
243357-004
Datasheet
5
I/O D
Input/Open-drain output pin requiring a pullup resistor
I/O
Bi-directional input/output pin
The signal description also includes the type of buffer used for a particular signal:
GTL+
Open-drain GTL+ interface signal
PCI
PCI bus interface signals
AGP
AGP bus interface signals
CMOS
The CMOS signals, depending on functional group, are 1.5V, 2.5V, or 3.3V.
3.1.2
Memory Signal Description
Table 2
provides descriptions of the memory interface signals.
Table 2. Memory Signals
Name
Type
Voltage
Description
MECC[7:0]
I/O
CMOS
V_3
Memory ECC Data:
These signals carry Memory ECC data during
access to DRAM.
ECC is not supported on the mobile module.
CSA[5:O]#
O
CMOS
V_3
Chip Select (SDRAM):
These pins activate the SDRAMs.
SDRAM
accepts any command when its CS# pin is active low.
DQMA[7:0]
O
CMOS
V_3
Input/Output Data Mask (SDRAM):
These pins act as synchronized
output enables during a read cycle and as a byte mask during a write
cycle.
MAB[9:0]#
MAB[10]
MAB[12:11]#
MAB[13]
O
CMOS
V_3
Memory Address (SDRAM):
This is the row and column address for
DRAM.
The 82443BX Host Bridge system controller has two identical
sets of address lines (MAA and MAB#). The mobile module supports
only the MAB set of address lines. For additional addressing features,
please refer to the
Intel
440BX AGPSet: 82443BX Host Bridge/
Controller Datasheet (Order Number: 290633-001).
MWEA#
O
CMOS
V_3
Memory Write Enable (SDRAM):
MWEA# should be used as the
write enable for the memory data bus.
SRASA#
O
CMOS
V_3
SDRAM Row Address Strobe (SDRAM):
When active low, this
signal latches Row Address on the positive edge of the clock. This
signal also allows Row access and pre-charge.
SCASA#
O
CMOS
V_3
SDRAM Column Address Strobe (SDRAM):
When active low, this
signal latches Column Address on the positive edge of the clock.
This
signal also allows Column access.
CKE[5:0]
O
CMOS
V_3
SDRAM Clock Enable (SDRAM):
SDRAM clock enable pin. When
these signals are deasserted, SDRAM enters power-down mode.
Each row is individually controlled by its own clock enable.
MD[63:0]
O
CMOS
V_3
Memory Data:
These signals are connected to the DRAM data bus.
They are not terminated on the mobile module.
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