參數(shù)資料
型號(hào)： celeron processor
廠商： Intel Corp.
英文描述： 32 bit Celeron Processor Mobile Module(32 位帶移動(dòng)模塊處理器)
中文描述： 32位賽揚(yáng)處理器的移動(dòng)模塊（32位帶移動(dòng)模塊處理器）
文件頁(yè)數(shù)： 14/64頁(yè)
文件大小： 799K
代理商： CELERON PROCESSOR
Celeron
Processor Mobile Module MMC-2
at 650 MHz, 600 MHz, 550 MHz, 500 MHz, and 450 MHz
8
Datasheet
243357-004
3.1.4
PCI Signals
Table 4
provides descriptions of the PCI signals.
Table 4. PCI Signal Description
Name
Type
Voltage
Description
AD[31:0]
I/O
PCI
V_3
Address/Data:
The standard PCI address and data lines. The
address is driven with FRAME# assertion, and data is driven or
received in the following clocks.
C/BE[3:0]
I/O
PCI
V_3
Command/Byte Enable:
The command is driven with FRAME#
assertion, and byte enables corresponding to supplied or requested
data are driven on the following clocks.
FRAME#
I/O
PCI
V_3
Frame:
Assertion indicates the address phase of a PCI transfer.
Negation indicates that the cycle initiator desires one more data
transfer.
DEVSEL#
I/O
PCI
V_3
Device Select:
The 82443BX Host Bridge drives this signal when a
PCI initiator is attempting to access DRAM.
DEVSEL# is asserted at
medium decode time.
IRDY#
I/O
PCI
V_3
Initiator Ready:
This signal is asserted when the initiator is ready for
data transfer.
TRDY#
I/O
PCI
V_3
Target Ready:
The signal is asserted when the target is ready for a
data transfer.
STOP#
I/O
PCI
V_3
Stop:
Asserted by the target to request the master to stop the current
transaction.
PLOCK#
I/O
PCI
V_3
Lock:
Indicates an exclusive bus operation and may require multiple
transactions to complete. When LOCK# is asserted, nonexclusive
transactions may proceed. The 82443BX supports lock for CPU
initiated cycles only. PCI initiated locked cycles are not supported.
REQ[4:0]#
I
PCI
V_3
PCI Request:
PCI master requests for PCI.
GNT[4:0]#
O
PCI
V_3
PCI Grant:
Permission is given to the master to use PCI.
PHOLD#
I
PCI
V_3
PCI Hold:
This signal comes from the expansion bridge. It is the
bridge request for PCI.
The 82443BX Host Bridge will drain the DRAM
write buffers, drain the processor-to-PCI posting buffers, and acquire
the host bus before granting the request via PHLDA#. This process
ensures that GAT timing is met for ISA masters.
The PHOLD#
protocol has been modified to include support for passive release.
PHLDA#
O
PCI
V_3
PCI Hold Acknowledge:
This signal is driven by the 82443BX Host
Bridge to grant PCI to the expansion bridge.
The PHLDA# protocol
has been modified to include support for passive release.
PAR
I/O
PCI
V_3
Parity:
A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
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