參數(shù)資料
型號(hào)： celeron processor
廠商： Intel Corp.
英文描述： 32 bit Celeron Processor Mobile Module(32 位帶移動(dòng)模塊處理器)
中文描述： 32位賽揚(yáng)處理器的移動(dòng)模塊（32位帶移動(dòng)模塊處理器）
文件頁(yè)數(shù)： 30/64頁(yè)
文件大?。?/td> 799K
代理商： CELERON PROCESSOR
Celeron
Processor Mobile Module MMC-2
at 650 MHz, 600 MHz, 550 MHz, 500 MHz, and 450 MHz
24
Datasheet
243357-004
Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition to
the Stop Grant state or the Quick Start state, where a Stop Grant Acknowledge bus cycle will be
issued. Deasserting STPCLK# will cause the processor to return to the Auto Halt state without
issuing a new Halt bus cycle.
The SMI# (System Management Interrupt) is recognized in the Auto Halt state. The return from the
SMI handler can be to either the Normal state or the Auto Halt state. See the
Intel Architecture
Software Developer's Manual, Volume III: System Programmer's Guide
for more information. No
Halt bus cycle is issued when returning to the Auto Halt state from System Management Mode
(SMM).
The FLUSH# signal is serviced in the Auto Halt state. After flushing the on-chip, the processor
will return to the Auto Halt state without issuing a Halt bus cycle. Transitions in the A20M# and
PREQ# signals are recognized while in the Auto Halt state.
4.4.1.3
Stop Grant State
The Celeron processor mobile module does not support the Stop Grant state.
The processor enters this mode with the assertion of the STPCLK# signal when it is configured for
Stop Grant state (via the A15# strapping option). The processor is still able to respond to snoop
requests and latch interrupts. Latched interrupts will be serviced when the processor returns to the
Normal state. Only one occurrence of each interrupt event will be latched. A transition back to the
Normal state can be made by the deassertion of the STPCLK# signal, or the occurrence of a stop
break event (a BINIT#, FLUSH#, or RESET# assertion).
The processor will return to the Stop Grant state after the completion of a BINIT# bus initialization
unless STPCLK# has been deasserted. RESET# assertion will cause the processor to immediately
initialize itself. However, the processor will stay in the Stop Grant state after initialization until
STPCLK# is deasserted. If the FLUSH# signal is asserted, the processor will flush the on-chip
caches and return to the Stop Grant state. A transition to the Sleep state can be made by the
assertion of the SLP# signal.
While in the Stop Grant state, assertions of SMI#, INIT#, INTR, and NMI (or LINT[1:0]) will be
latched by the processor. These latched events will not be serviced until the processor returns to the
Normal state. Only one of each event will be recognized upon return to the Normal state.
4.4.1.4
Quick Start State
This is a mode entered by the processor with the assertion of the STPCLK# signal when it is
configured for the Quick Start state (via the A15# strapping option). In the Quick Start state the
processor is only capable of acting on snoop transactions generated by the PSB priority device.
Because of its snooping behavior, Quick Start can only be used in single processor configurations.
A transition to the Deep Sleep state can be made by stopping the clock input to the processor. A
transition back to the Normal state (from the Quick Start state) is made only if the STPCLK# signal
is deasserted.
While in this state the processor is limited in its ability to respond to input. It is incapable of
latching any interrupts, servicing snoop transactions from symmetric bus masters, or responding to
FLUSH# and BINIT# assertions. In the Quick Start state, the processor will not respond properly
to any input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal changes,
then the behavior of the processor will be unpredictable. No serial interrupt messages may begin or
be in progress while the processor is in the Quick Start state.
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