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| 型號(hào)： | celeron processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit Celeron Processor Mobile Module(32 位帶移動(dòng)模塊處理器) |
| 中文描述： | 32位賽揚(yáng)處理器的移動(dòng)模塊（32位帶移動(dòng)模塊處理器） |
| 文件頁數(shù)： | 17/64頁 |
| 文件大小： | 799K |
| 代理商： | CELERON PROCESSOR |
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Celeron
Processor Mobile Module MMC-2
at 650 MHz, 600 MHz, 550 MHz, 500 MHz, and 450 MHz
243357-004
Datasheet
11
3.1.6
Power Management Signals
Table 6
provides descriptions of the power management signals. The SM_CLK and SM_DATA
signals refer to the two-wire serial SMBus interface. Although this interface is currently used
solely for the digital thermal sensor, the SMBus contains reserved serial addresses for future use.
NOTE:
V_3ALWAYS is a 3.3-V supply and is generated whenever V_DC is available and supplied to the
PIIX4E/M resume well.
Table 6. Power Management Signal Descriptions
Name
Type
Voltage
Description
SUS_STAT1#
I
CMOS
V_3ALWAYS
Suspend Status:
This signal connects to the SUS_STAT1#
output of PIIX4E/M. It provides information on host clock status,
and it is asserted during all suspend states.
VR_ON
I
CMOS
V_3
VR_ON:
Voltage regulator ON.
This 3.3-V (5.0-V tolerant) signal
controls the operation of the voltage regulator.
VR_ON should
be generated as a function of the PIIX4E/M SUSB# signal,
which is used for controlling the “Suspend State B” voltage
planes. This signal should be driven by a digital signal with a
rise/fall time of less than or equal to 1
μ
S. (V
IL,max
=0.4V, V
IH,min
=3.0V.)
VR_PWRGD
O
V_3
VR_PWRGD:
This signal is driven high by the mobile module to
indicate that the voltage regulator is stable. The signal is pulled
low using a 100-K resistor when inactive.
It can be used in some
combination to generate the system PWRGOOD signal.
BXPWROK
I
CMOS
V_3
Power OK to BX:
This signal must go active at least 1 mS after
the V_3 power rail is stable, and 1 mS prior to deassertion of
PCIRST#.
SM_CLK
I/O D
CMOS
V_3
Serial Clock:
This clock signal is used on the SMBus interface
to the digital thermal sensor.
SM_DATA
I/O D
CMOS
V_3
Serial Data:
Open-drain data signal on the SMBus interface to
the digital thermal sensor.
ATF_INT#
O D
CMOS
V_3
ATF Interrupt:
This signal is an open-drain output signal of the
digital thermal sensor.
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