參數(shù)資料
型號(hào)： celeron processor
廠商： Intel Corp.
英文描述： 32 bit Celeron Processor Mobile Module(32 位帶移動(dòng)模塊處理器)
中文描述： 32位賽揚(yáng)處理器的移動(dòng)模塊（32位帶移動(dòng)模塊處理器）
文件頁(yè)數(shù)： 27/64頁(yè)
文件大?。?/td> 799K
代理商： CELERON PROCESSOR
Celeron
Processor Mobile Module MMC-2
at 650 MHz, 600 MHz, 550 MHz, 500 MHz, and 450 MHz
243357-004
Datasheet
21
is always device #0, AD11 will never be asserted during PCI configuration cycles as an IDSEL.
The 82443BX reserves AD12 for the AGPbus. Thus, AD13 is the first available address line usable
as an IDSEL. Intel recommends that AD18 be used by the PIIX4E/M.
4.3.4
AGP Interface
The 82443BX Host Bridge system controller is compliant with the
AGP Interface Specification
Revision 2.0
, which supports an asynchronous AGP interface coupling to the 82443BX core
frequency. The AGP interface can achieve real data throughput in excess of 500 MB per second
using an AGP 2X graphics device. Actual bandwidth may vary depending on specific hardware
and software implementations.
4.4
Power Management
4.4.1
Clock Control Architecture
The clock control architecture has been optimized for notebook designs. The clock control
architecture consists of seven different clock states: Normal, Stop Grant, Auto Halt, Quick Start,
HALT/Grant Snoop, Sleep, and Deep Sleep states. The Auto Halt state provides a low-power clock
state that can be controlled through the software execution of the HLT instruction. The Quick Start
state provides a very low-power, low-exit latency clock state that can be used for hardware
controlled "idle" states. The Deep Sleep state provides an extremely low-power state that can be
used for Power-On-Suspend states, which is an alternative to shutting off the processor's power.
The exit latency of the Deep Sleep state is 30
μ
S. The Stop Grant state and the Quick Start clock
state are mutually exclusive. For example, a strapping option on signal A15# chooses which state is
entered when the STPCLK# signal is asserted. Strapping the A15# signal to ground at Reset
enables the Quick Start state. Otherwise, asserting the STPCLK# signal puts the processor into the
Stop Grant state.
Figure 3
illustrates the clock control architecture. Performing state transitions not shown in
Figure
3
are neither recommended nor supported.
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