- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379803 > CD1865 (Intel Corp.) Intelligent Eight-Channel Communications Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁(yè)數(shù)： | 55/150頁(yè) |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)當(dāng)前第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)
Intelligent Eight-Channel Communications Controller
—
CD1865
Datasheet
55
At this point, the system waits endlessly unless the bus cycle terminates. The best method is to
connect the ACKOUT* of the last CD1865 in the chain to a bus-error input on the host. If there are
multiple CD1865s that are not cascaded, the ACKOUT* signals should be OR
’
ed together through
a gate or a PAL.
If an acknowledgment occurs and the value on the address bus does not match any of the Match
registers, the first CD1865 in the chain does not pass it along or assert DTACK* and the system
waits endlessly unless there is a bus time-out or other mechanism to detect this condition. In either
of these circumstances, the
‘
value
’
on the data bus is likely to be FFh because the bus is floating
(this is system dependent). To make a robust design, do not use FFh as a valid Global Service
Vector register (GSVR) value. If daisy chaining is not enabled, then the CD1865 returns a vector of
‘
00
’
for invalid acknowledgments.
6.4.1
Interfacing to 80X86-Family Processors
The Intel 80X86 family processors often use the 8259A as the interrupt controller, which supplies
its own vector during the INTA cycle. The easiest way to interface the CD1865 to an Intel
processor is by Mixed mode, as described in
Section 5.5
.
There is one
‘
bug
’
in the 8259A to be aware of. The 8259A can change the prioritizing of its eight
inputs, which can result in one of its acknowledge outputs going low briefly (~30 ns) if an input
changes at a certain time. This typically occurs if a higher-priority input to the 8259A asserts when
the 8259A is about to issue an acknowledge to a lower-priority device. If this occurs at the
beginning of a cycle, this brief pulse can cause the CD1865 (and other devices) to malfunction. Be
sure that this does not occur. See
Intel 8259A Data Sheet
for details.
6.4.2
Interfacing to 680X0-Family Processors
The 68000-family interface is quite straightforward. The three service request lines go through a
priority encoder to the 680X0 IPL inputs. The CD1865s ACKIN* pin is driven by a decoder.
When the 680X0 performs an Interrupt Acknowledge cycle, it drives its address lines A1, A2, and
A3 with a three-bit value indicating the level being serviced. The other address lines are set to a 1.
If the level being serviced corresponds to a level assigned to the CD1865, external decoding logic
should assert the CD1865 ACKIN* pin. The value on address lines A0 to A7 is programmed into
the , so the CD1865 recognizes the acknowledgment and proceeds as described in the Service
Request
Section 5.3.1
.
All CD1865 service requests can also be routed to a single interrupt level by using a Mixed-mode
interface, as described in
Section 5.5
.
6.4.3
Interfacing to the VME Bus
The CD1865 can be directly interfaced to the VME bus, and only requires a small amount of logic
to complete the interface. This is necessary because service request acknowledgment works
differently on the VME bus than on the CD1865. VME defines seven levels of interrupts; each
level can be shared among multiple VME cards. During an Interrupt Acknowledge cycle, the VME
bus provides three bits on the address bus, indicating the level being acknowledged (A1-A3). Each
VME card must pass along an interrupt on all levels it is not using but the CD1865 does not
automatically pass an interrupt acknowledgment.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD22100 | CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating) |
| CD22100E | CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating) |
| CD22100F | CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating) |
| CD22101 | CMOS 4 x 4 x 2 Crosspoint Switch with Control Memory |
| CD22101E | CMOS 4 x 4 x 2 Crosspoint Switch with Control Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD1865N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1865P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1867N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。