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參數(shù)資料
| 型號(hào)： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁(yè)數(shù)： | 51/150頁(yè) |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
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Intelligent Eight-Channel Communications Controller
—
CD1865
Datasheet
51
6.2.5
Maximum Throughput Limits
The CD1865 is internally a fully static, synchronous design. Consequently, the maximum data rate
handled by CD1865 is determined by the clock speed at which it is operating. There are a fixed
number of CD1865 processor cycles required to process each bit and character; a slower CD1865
processor rate equates to a slower bit rate. The minimum clock frequency required can be
determined by the data rate needed for support.
In general, the CD1865 can maintain 100% full-duplex throughput when divisors of 16 or greater
are used. For a given master clock frequency, this limitation can be used to determine the
maximum bit rate at which the system can sustain 100% throughput on both receive and transmit.
Divisors as small as 12 can be used, however a degradation in throughput is observed. This
degradation is seen as gaps between transmit characters and are, in effect, extra long stop bits. This
is a fail-safe condition. Divisors smaller than 12 can work in an application if less than eight
channels are enabled.
6.3
CD1865 Basic Bus Interface and Addressing
The CD1865 is addressed through an active-low Chip Select (CS*) in conjunction with seven
Address Inputs A[0:6] that are mapped CD1865 internal addresses in two addressing modes
—
global and channel. In Channel Addressing mode, the bits defining the channel to be accessed are
provided from the Channel Access register (CAR) within the CD1865.
The most-significant Address Input (A6) performs the selection between global- and channel-
specific addresses. If this bit is a
‘
1
’
, the address is global, and is not associated with any specific
channel. If this bit is a
‘
0
’
, the address is channel-related.
With the exception of the FIFOs, all channel-specific registers are accessed by first setting the
required channel number in the low-three bits of the Channel Access register. FIFOs can only be
accessed within the context of a service routine. Attempting to force access to a particular FIFO by
setting the CAR causes unpredictable and incorrect results. Within the context of a service request,
the effective channel access value is automatically controlled by the CD1865, thus the CAR should
not be modified by the host system during service-request processing.
The advantage of this method is that the host never performs any address computation to access the
CD1865 during service requests. Because only the registers specific for the active channel (that is,
the one being serviced) are accessible to the host within a service request routine. An automatic
indexing feature handles this, thus avoiding any burden on the host. Refer to
Section 9.3
on
Indexed Indirect registers for details.
6.3.1
Intel
Versus Motorola
Interface Signals and Addressing
The CD1865 supports two bus handshake methods. One is patterned after the Motorola 680X0-
family processors, and the other after Intel 80X86-bus interfaces. bus interface selection is
achieved by the INTEL/MOT* signal. When this signal is
‘
high
’
, the Intel bus interface is selected,
and when this signal is
‘
low
’
, the Motorola bus interface is selected. This selection affects the
logical meaning of two pins, but has no effect on bus timing.
The two signals having dual meaning are RD* versus DS*, and WR* versus R/W*. When the Intel
bus interface is selected, these two pins function as RD* and WR*. These pins can be connected to
either the IOR* and IOW*, or to MEMRD* and MEMWR* depending whether the CD1865 is
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