- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄379803 > CD1865 (Intel Corp.) Intelligent Eight-Channel Communications Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁(yè)數(shù)： | 110/150頁(yè) |
| 文件大小： | 871K |
| 代理商： | CD1865 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)當(dāng)前第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)
CD1865
—
Intelligent Eight-Channel Communications Controller
110
Datasheet
9.3.3
Receive Character Status Register
This register accesses the status information for the current receive character.
Multiple errors in 1 byte are possible because the CD1865 evaluates the character bit-by-bit as it
receives it. For example, a parity error is detected and flagged before a framing error. If a character
is received with every bit (including the stop bit) equal to a
‘
0
’
, it is marked as a line-break. If some
bits are a
‘
1
’
, but the Stop bit is
‘
missing
’
a
‘
0
’
, it is marked as a framing error. If odd parity is set
and the bits received are all zeroes, it is marked as both a break character and a parity error. In
addition to any other bits, the Overrun bit is set if an overrun has occurred. Any attempt to write to
this register causes unpredictable results.
Register Name:
Register Description: Receive Character Status Register
Default Value: 0
Access: Read Only
Bit 7
Bit 6
8-Bit Hex Address: $7A
Intel Hex Address: $F4
Motorola Hex Address: $F5
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Time-out
SC Det2
SC Det1
SC Det0
Break
PE
FE
OE
Bit
Description
Bit 7
Time-out:
Indicates that the Receive FIFO is empty, and no data has been received within the receive time-
out period. There is no data character associated with this status and no other status bits are valid if the Time-
out bit is set. Must be
‘
armed
’
by the NNDT bit in .
Bits 6:4
Special Character Detect (SCD0-2):
NOTE:
No special-character match is performed if any type of error occurs. The second character of a two-
character sequence cannot cause a receiver overrun.
Bit 3
Break:
Indicates that a break has been detected.
Bit 2
Parity Error:
Indicates that a parity error has been detected.
Bit 1
Framing Error:
Indicates that a bad Stop bit has been detected.
Bit 0
Overrun Error:
Indicates that new data has arrived but the CD1865 FIFO and Holding registers
are full. The new data is lost and the overrun indication is flagged on the last character received
before the overrun occurred.
SCD2
SCD1
SCD0
Status
0
0
0
None detected
0
0
1
Special Character 1 or Special Character 1 and 3 sequence matched
(only if Special Character 1 and 3 sequence is enabled).
0
1
0
Special Character 2 or Special Character 2 and 4 sequence matched
(only if Special Character 1 and 3 sequence is enabled).
0
1
1
Special Character 3 (only if Special Character 1 and 3 sequence is not
enabled).
1
0
0
Special Character 4 (only if Special Character 2 and 4 sequence is not
enabled).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD22100 | CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating) |
| CD22100E | CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating) |
| CD22100F | CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating) |
| CD22101 | CMOS 4 x 4 x 2 Crosspoint Switch with Control Memory |
| CD22101E | CMOS 4 x 4 x 2 Crosspoint Switch with Control Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD1865N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1865P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1867N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。