參數(shù)資料
型號(hào): CD1865
廠商: Intel Corp.
英文描述: Intelligent Eight-Channel Communications Controller
中文描述: 智能八通道通信控制器
文件頁(yè)數(shù): 20/150頁(yè)
文件大小: 871K
代理商: CD1865
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)當(dāng)前第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)
CD1865
Intelligent Eight-Channel Communications Controller
20
Datasheet
serial I/O subsystem for the presence of data. If data is present, the CD1865 determines which
channel it is on, and whether it is good or erroneous. Thus, using the CD1865, the host-peripheral
interface is easier to implement, faster, and more efficient.
5.2
Internal Operation
The internal architecture of the CD1865 is shown in
Figure 2
. The foundation of the design is a
custom-designed CPU that Intel has developed especially for this application. This CPU is
optimized for bit-oriented tasks associated with UART functions, and it has a set of registers for
each channel, arranged in a register window architecture. These registers and the ALU are eight
bits wide. The CD1865 processor has a 16-bit instruction word that it retrieves from an on-device
ROM. Every instruction is one-word long and executed in one-clock cycle.
Whenever an internal interrupt occurs (from a bit engine), the CD1865 processor automatically
switches context to that channel
s block of registers. No time is lost in saving any machine state.
The CD1865 processor executes the instructions necessary to handle that bit (typically three to six
instructions) and then returns to the context it was in prior to the internal interrupt. All internal
interrupts are at the same priority level; the interrupt handler block ensures fair-share access across
channels.
Each channel
s serial interface logic consists of a receive-bit engine, a transmit-bit engine, a
receive-baud-rate generator, a transmit-baud-rate generator, and a timer. The receive-bit engine
samples the state of the RxD pin at the time indicated by the receive-baud-rate generator, and it
reports this value to the CD1865 processor as an interrupt. The transmit-bit engine works in a
similar manner. At the baud rate tick, it outputs the next bit and generates an interrupt to the
CD1865 processor requesting the following bit.
The baud-rate generators are 16-bit dividers that operate from a master clock, which is the system
clock divided by 16. All baud-rate generators are independent, so a channel can send and receive at
any speed. In addition to the baud-rate generators, there are two channel timers for each channel.
One is an 8-bit divider, operating off the master prescaler timer tick. This timer is used to time-out
partially full FIFOs to avoid
stale
data. The other is used to time embedded delays in the transmit
data stream.
All eight channels are continuously scanned by internal logic that generates interrupts to the
CD1865 processor in a
fair
manner. This fair-share interrupt feature is the same as the mechanism
used to share service requests across multiple devices. Whenever two or more channels are
contending for interrupt service, the channel that is serviced first does not assert again until all
other currently pending channels are serviced. This prevents a fast, 64-kbps channel from
demanding service from a slow 1200-bps channel, yet it allows the faster channel the additional
service it needs to support its higher speed. This allows more overall throughput than a
round-
robin
or an
equal-access
method would provide.
Service requests for the host are handled by fast, dedicated logic on each of the three levels
provided. Whenever the CD1865 processor detects a condition requiring external-host service, it
queues the request with the service-request machine for that level. This machine asserts the
External Request pin, and it monitors for a service acknowledgment of the same level. When a
service acknowledgment is sensed, the machine automatically provides the vector to the host and
sets up the internal context of the CD1865 for service. Upon completion of the service, the machine
restores the normal context. The queue for service requests is two deep, so in a busy system there
can be another request immediately pending when the first one is completed. This method avoids
any delay between requests, and improves overall efficiency.
相關(guān)PDF資料
PDF描述
CD22100 CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating)
CD22100E CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating)
CD22100F CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating)
CD22101 CMOS 4 x 4 x 2 Crosspoint Switch with Control Memory
CD22101E CMOS 4 x 4 x 2 Crosspoint Switch with Control Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CD1865N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
CD1865P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
CD1866N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
CD1866P 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC
CD1867N 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC