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參數(shù)資料
| 型號： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁數(shù)： | 20/150頁 |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
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CD1865
—
Intelligent Eight-Channel Communications Controller
20
Datasheet
serial I/O subsystem for the presence of data. If data is present, the CD1865 determines which
channel it is on, and whether it is good or erroneous. Thus, using the CD1865, the host-peripheral
interface is easier to implement, faster, and more efficient.
5.2
Internal Operation
The internal architecture of the CD1865 is shown in
Figure 2
. The foundation of the design is a
custom-designed CPU that Intel has developed especially for this application. This CPU is
optimized for bit-oriented tasks associated with UART functions, and it has a set of registers for
each channel, arranged in a register window architecture. These registers and the ALU are eight
bits wide. The CD1865 processor has a 16-bit instruction word that it retrieves from an on-device
ROM. Every instruction is one-word long and executed in one-clock cycle.
Whenever an internal interrupt occurs (from a bit engine), the CD1865 processor automatically
switches context to that channel
’
s block of registers. No time is lost in saving any machine state.
The CD1865 processor executes the instructions necessary to handle that bit (typically three to six
instructions) and then returns to the context it was in prior to the internal interrupt. All internal
interrupts are at the same priority level; the interrupt handler block ensures fair-share access across
channels.
Each channel
’
s serial interface logic consists of a receive-bit engine, a transmit-bit engine, a
receive-baud-rate generator, a transmit-baud-rate generator, and a timer. The receive-bit engine
samples the state of the RxD pin at the time indicated by the receive-baud-rate generator, and it
reports this value to the CD1865 processor as an interrupt. The transmit-bit engine works in a
similar manner. At the baud rate tick, it outputs the next bit and generates an interrupt to the
CD1865 processor requesting the following bit.
The baud-rate generators are 16-bit dividers that operate from a master clock, which is the system
clock divided by 16. All baud-rate generators are independent, so a channel can send and receive at
any speed. In addition to the baud-rate generators, there are two channel timers for each channel.
One is an 8-bit divider, operating off the master prescaler timer tick. This timer is used to time-out
partially full FIFOs to avoid
‘
stale
’
data. The other is used to time embedded delays in the transmit
data stream.
All eight channels are continuously scanned by internal logic that generates interrupts to the
CD1865 processor in a
‘
fair
’
manner. This fair-share interrupt feature is the same as the mechanism
used to share service requests across multiple devices. Whenever two or more channels are
contending for interrupt service, the channel that is serviced first does not assert again until all
other currently pending channels are serviced. This prevents a fast, 64-kbps channel from
demanding service from a slow 1200-bps channel, yet it allows the faster channel the additional
service it needs to support its higher speed. This allows more overall throughput than a
‘
round-
robin
’
or an
‘
equal-access
’
method would provide.
Service requests for the host are handled by fast, dedicated logic on each of the three levels
provided. Whenever the CD1865 processor detects a condition requiring external-host service, it
queues the request with the service-request machine for that level. This machine asserts the
External Request pin, and it monitors for a service acknowledgment of the same level. When a
service acknowledgment is sensed, the machine automatically provides the vector to the host and
sets up the internal context of the CD1865 for service. Upon completion of the service, the machine
restores the normal context. The queue for service requests is two deep, so in a busy system there
can be another request immediately pending when the first one is completed. This method avoids
any delay between requests, and improves overall efficiency.
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| CD1865N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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| CD1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1867N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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