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參數(shù)資料
| 型號： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁數(shù)： | 128/150頁 |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
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CD1865
—
Intelligent Eight-Channel Communications Controller
128
Datasheet
10.4
Index of Timing Information
10.5
AC Electrical Characteristics
Internally, the CD1865 is a fully clocked design; however, the hardware interface to the CD1865
may be either unclocked or clocked. An unclocked interface is generally easier to implement,
especially if the CD1865 and its host are operating at different clock speeds. A clocked interface
may be faster in some applications.
10.5.1
Clocked Bus Interface
Data transfers to or from the device occur in two steps. The first step occurs during the clock-low
time. If the read/write state machine detects that it is time to do a cycle, it acquires the internal bus.
The second step, that of actually transferring the data, occurs during the clock-high time. The cycle
is complete at the end of the clock-high time.
The read/write state machine determines that it is time to do a cycle when there is a falling edge on
the clock and both CS* and DS* are low. There is a specified setup time which must be met to
guarantee that the cycle begins. If this setup is not met, the cycle occurs one clock later. If the cycle
is recognized, arbitration for the internal bus is done during the clock-low time. Addresses (and
data, if a write cycle) must meet another setup time specification to the rising edge of the clock for
the actual data transfer to occur properly during the clock-high time. In addition, the addresses
must remain valid throughout the clock-high time, as specified. If the cycle is a write cycle, data
must remain valid as specified. If the cycle is a read cycle, data is guaranteed valid for a specified
time after the rising edge of the clock.
Figure
Title
Page
Figure 29
“
Clocked Bus Interface Reset
”
130
Figure 30
“
Clocked Bus Interface Clocks
”
131
Figure 31
“
Clocked Bus Interface Read Cycle, Motorola
-Style Handshake
”
131
Figure 32
“
Clocked Bus Interface Service Acknowledgment Cycle, Motorola
-Style
Handshake
”
132
Figure 33
“
Clocked Bus Interface Write Cycle, Motorola
-Style Handshake
”
133
Figure 34
“
Clocked Bus Interface Read Cycle, Intel
-Style Handshake
”
134
Figure 35
“
Clocked Bus Interface Service Acknowledgment Cycle, Intel
-Style
Handshake
”
135
Figure 36
“
Clocked Bus Interface Write Cycle, Intel
-Style Handshake
”
136
Figure 37
“
Unclocked Bus Interface Read Cycle, Motorola
-Style Handshake
”
139
Figure 38
“
Unclocked Bus Interface Service Acknowledgment Cycle, Motorola
-Style
Handshake
”
140
Figure 39
“
Unclocked Bus Interface Write Cycle, Motorola
-Style Handshake
”
141
Figure 40
“
Unclocked Bus Interface Read Cycle, Intel
-Style Handshake
”
142
Figure 41
“
Unclocked Bus Interface Service Acknowledgment Cycle, Intel
-Style
Handshake
”
143
Figure 42
“
Unclocked Bus Interface Write Cycle, Intel
-Style Handshake
”
144
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD1865N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1865P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1867N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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