- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379803 > CD1865 (Intel Corp.) Intelligent Eight-Channel Communications Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁(yè)數(shù)： | 52/150頁(yè) |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)當(dāng)前第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)
CD1865
—
Intelligent Eight-Channel Communications Controller
52
Datasheet
mapped into memory or I/O space. These pins then serve to select the CD1865, and when either is
active (along with CS* or ACKIN*) the CD1865 considers itself selected. CS* and ACKIN* must
never be active at the same time.
When the Motorola bus interface is selected, these two signals function as DS* and R/W*. DS*
must be asserted (along with CS* or ACKIN*) for all types of cycles, and R/W* should be low
when writing to the device.
In either case, the choice of bus interface is entirely up to the user. This feature is for user
convenience, and to accommodate the address and bus-control logic that are used. The CD1865 has
an 8-bit data bus, and it is a common practice (when connecting 8-bit peripherals to 16- or 32-bit
systems) to connect them to only one lane, or 1-byte position. Thus, the CD1865 registers only
appear in the host
’
s address space at every other byte address. The most common practice is to
connect the CD1865 to the portion of the data bus labelled D0
–
D7. For the little-endian processors,
such as Intel
’
s, the CD1865 appears at even addresses (A0 = 0). For big-endian processors, such as
Motorola
’
s, the CD1865 appears at odd addresses.
6.3.2
Unclocked Versus Clocked Bus Interface
Depending on the type and speed of the host processor, another important choice is determining
whether the system bus interface will be clocked or unclocked with the host CPU clock. Because
there is a single clock for both the bus interface and bit-rate generation, the decision to use either
Clocked or Unclocked bus interface is affected by whether exact bit rates are required. Most
applications do not require exact bit rates, and operate with rates varying by one percent or so. If
exact bit rates are required, the clock speed must be a baud-rate multiple.
One method of bus interfacing may be preferable to another in certain applications. Although the
easiest way to interface to the CD1865 is by using the unclocked handshake supplied by DTACK*,
in some cases it may be better to design a clocked interface. The latter is true if the host system is
running at the same clock speed (or a multiple) of the CD1865 speed.
Unclocked Bus Interface
An Unclocked bus interface is the easiest interface to implement. Simply connect the address, data,
and control lines in the customary manner, and use DTACK* to control the number of wait states
either by connecting it to the processor
’
s DTACK* (if it has one), or by feeding into a wait-state
generator.
Figure 17 on page 53
shows a typical Unclocked bus interface.
The maximum bus cycle time is two clock periods plus 10 ns, though typically less because this
specification is based on worst-case internal synchronization delays. Using DTACK* saves time;
however, it is permissible to hard-wire the wait-state generator for the maximum time.
Clocked Bus Interface
The CD1865 bus interface is controlled by a state machine that samples on the falling edge of the
clock. External strobes (CS*, DS*, and R/W*; or CS*, and RD* or WR*) that meet the setup time
requirement cause a bus cycle to begin. The external interface can be designed to meet these setup
time requirements, and to have shorter CD1865 access cycles.
Figure 18 on page 54
shows a
typical Clocked bus interface.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD22100 | CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating) |
| CD22100E | CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating) |
| CD22100F | CMOS 4 x 4 Crosspoint Switch with Control Memory High-Voltage Type (20V Rating) |
| CD22101 | CMOS 4 x 4 x 2 Crosspoint Switch with Control Memory |
| CD22101E | CMOS 4 x 4 x 2 Crosspoint Switch with Control Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD1865N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1865P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1867N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。