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參數(shù)資料
| 型號： | CD1865 |
| 廠商： | Intel Corp. |
| 英文描述： | Intelligent Eight-Channel Communications Controller |
| 中文描述： | 智能八通道通信控制器 |
| 文件頁數(shù)： | 52/150頁 |
| 文件大?。?/td> | 871K |
| 代理商： | CD1865 |
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CD1865
—
Intelligent Eight-Channel Communications Controller
52
Datasheet
mapped into memory or I/O space. These pins then serve to select the CD1865, and when either is
active (along with CS* or ACKIN*) the CD1865 considers itself selected. CS* and ACKIN* must
never be active at the same time.
When the Motorola bus interface is selected, these two signals function as DS* and R/W*. DS*
must be asserted (along with CS* or ACKIN*) for all types of cycles, and R/W* should be low
when writing to the device.
In either case, the choice of bus interface is entirely up to the user. This feature is for user
convenience, and to accommodate the address and bus-control logic that are used. The CD1865 has
an 8-bit data bus, and it is a common practice (when connecting 8-bit peripherals to 16- or 32-bit
systems) to connect them to only one lane, or 1-byte position. Thus, the CD1865 registers only
appear in the host
’
s address space at every other byte address. The most common practice is to
connect the CD1865 to the portion of the data bus labelled D0
–
D7. For the little-endian processors,
such as Intel
’
s, the CD1865 appears at even addresses (A0 = 0). For big-endian processors, such as
Motorola
’
s, the CD1865 appears at odd addresses.
6.3.2
Unclocked Versus Clocked Bus Interface
Depending on the type and speed of the host processor, another important choice is determining
whether the system bus interface will be clocked or unclocked with the host CPU clock. Because
there is a single clock for both the bus interface and bit-rate generation, the decision to use either
Clocked or Unclocked bus interface is affected by whether exact bit rates are required. Most
applications do not require exact bit rates, and operate with rates varying by one percent or so. If
exact bit rates are required, the clock speed must be a baud-rate multiple.
One method of bus interfacing may be preferable to another in certain applications. Although the
easiest way to interface to the CD1865 is by using the unclocked handshake supplied by DTACK*,
in some cases it may be better to design a clocked interface. The latter is true if the host system is
running at the same clock speed (or a multiple) of the CD1865 speed.
Unclocked Bus Interface
An Unclocked bus interface is the easiest interface to implement. Simply connect the address, data,
and control lines in the customary manner, and use DTACK* to control the number of wait states
either by connecting it to the processor
’
s DTACK* (if it has one), or by feeding into a wait-state
generator.
Figure 17 on page 53
shows a typical Unclocked bus interface.
The maximum bus cycle time is two clock periods plus 10 ns, though typically less because this
specification is based on worst-case internal synchronization delays. Using DTACK* saves time;
however, it is permissible to hard-wire the wait-state generator for the maximum time.
Clocked Bus Interface
The CD1865 bus interface is controlled by a state machine that samples on the falling edge of the
clock. External strobes (CS*, DS*, and R/W*; or CS*, and RD* or WR*) that meet the setup time
requirement cause a bus cycle to begin. The external interface can be designed to meet these setup
time requirements, and to have shorter CD1865 access cycles.
Figure 18 on page 54
shows a
typical Clocked bus interface.
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相關代理商/技術參數(shù) |
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|---|---|
| CD1865N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1865P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1866P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| CD1867N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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